參數(shù)資料
型號: TMX320C6412GNZ
廠商: Texas Instruments, Inc.
英文描述: Signal Processor
中文描述: 信號處理器
文件頁數(shù): 90/159頁
文件大小: 1989K
代理商: TMX320C6412GNZ
Clock PLL
90
April 2003 Revised June 2004
SPRS219D
2.14
Clock PLL
Most of the internal C64x
DSP clocks are generated from a single source through the CLKIN pin. This source
clock either drives the PLL, which multiplies the source clock frequency to generate the internal CPU clock,
or bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 28
shows the external PLL circuitry for either x1 (PLL bypass) or other PLL multiply modes.
To minimize the clock jitter, a single clean power supply should power both the C64x
DSP device and the
external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input
clock timing requirements, see the
input and output clocks
electricals section.
Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source
must meet the DSP requirements in this data sheet (see the
electrical characteristics over recommended
ranges of supply voltage and operating case temperature
table and the
input and output clocks
electricals
section).
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