參數(shù)資料
型號： TMX320C6412GNZ
廠商： Texas Instruments, Inc.
英文描述： Signal Processor
中文描述： 信號處理器
文件頁數(shù)： 36/159頁
文件大小： 1989K
代理商： TMX320C6412GNZ
Peripheral Register Descriptions
36
April 2003 Revised June 2004
SPRS219D
Table 19. Ethernet MAC (EMAC) Control Registers (Continued)
HEX ADDRESS RANGE
REGISTER NAME
ACRONYM
01C8 0160
MACCONTROL
MAC Control Register
01C8 0164
MACSTATUS
MAC Status Register (RXQOSACT field is reserved.)
01C8 0168 01C8 016C
Reserved
01C8 0170
TXINTSTATRAW
Transmit Interrupt Status (Unmasked) Register
01C8 0174
TXINTSTATMASKED
Transmit Interrupt Status (Masked) Register
01C8 0178
TXINTMASKSET
Transmit Interrupt Mask Set Register
01C8 017C
TXINTMASKCLEAR
Transmit Interrupt Mask Clear Register
01C8 0180
MACINVECTOR
MAC Input Vector Register
01C8 0184 01C8 018F
Reserved
01C8 0190
RXINTSTATRAW
Receive Interrupt Status (Unmasked) Register
(Bits 71 are reserved.)
01C8 0194
RXINTSTATMASKED
Receive Interrupt Status (Masked) Register
(Bits 71 are reserved.)
01C8 0198
RXINTMASKSET
Receive Interrupt Mask Set Register
(Bits 71 are reserved and only support writes of 0.)
01C8 019C
RXINTMASKCLEAR
Receive Interrupt Mask Clear Register
(Bits 71 are reserved and only support writes of 0.)
01C8 01A0
MACINTSTATRAW
MAC Interrupt Status (Unmasked) Register
01C8 01A4
MACINTSTATMASKED
MAC Interrupt Status (Masked) Register
01C8 01A8
MACINTMASKSET
MAC Interrupt Mask Set Register
01C8 01AC
MACINTMASKCLEAR
MAC Interrupt Mask Clear Register
01C8 01B0
MACADDRL0
MAC Address Channel 0 Lower Byte Register
01C8 01B4
MACADDRL1
01C8 01B8
MACADDRL2
01C8 01BC
MACADDRL3
01C8 01C0
MACADDRL4
Reserved. Do not write.
01C8 01C4
MACADDRL5
01C8 01C8
MACADDRL6
01C8 01CC
MACADDRL7
01C8 01D0
MACADDRM
MAC Address Middle Byte Register
01C8 01D4
MACADDRH
MAC Address High Bytes Register
01C8 01D8
MACHASH1
MAC Address Hash 1 Register
01C8 01DC
MACHASH2
MAC Address Hash 2 Register
01C8 01E0
BOFFTEST
Backoff Test Register
01C8 01E4
TPACETEST
Transmit Pacing Test Register
01C8 01E8
RXPAUSE
Receive Pause Timer Register
01C8 01EC
TXPAUSE
Transmit Pause Timer Register
01C8 01F0 01C8 01FF
Reserved
01C8 0200 01C8 05FF
(see Table 110)
EMAC Statistics Registers
01C8 0600
TX0HDP
Transmit Channel 0 DMA Head Descriptor Pointer Register
01C8 0604
TX1HDP
Transmit Channel 1 DMA Head Descriptor Pointer Register
01C8 0608
TX2HDP
Transmit Channel 2 DMA Head Descriptor Pointer Register
01C8 060C
TX3HDP
Transmit Channel 3 DMA Head Descriptor Pointer Register
01C8 0610
TX4HDP
Transmit Channel 4 DMA Head Descriptor Pointer Register
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