參數(shù)資料
型號： TMX320C6412GNZ
廠商： Texas Instruments, Inc.
英文描述： Signal Processor
中文描述： 信號處理器
文件頁數(shù)： 64/159頁
文件大小： 1989K
代理商： TMX320C6412GNZ
Terminal Functions
64
April 2003 Revised June 2004
SPRS219D
Table 210. Terminal Functions
SIGNAL
IPD/
IPU
NAME
GDK/
GNZ
TYPE
DESCRIPTION
CLOCK/PLL CONFIGURATION
CLKIN
AC2
I
IPD
Clock Input. This clock is the input to the on-chip PLL.
CLKOUT4/GP0[1]§
D6
I/O/Z
IPD
Clock output at 1/4 of the device speed (
O/Z
) [default] or this pin can be programmed as
a GP0 1 pin (
I/O/Z
).
CLKOUT6/GP0[2]§
C6
I/O/Z
IPD
Clock output at 1/6 of the device speed (
O/Z
) [default] or this pin can be programmed as
a GP0 2 pin (
I/O/Z
).
CLKMODE1
AE4
I
IPD
Clock mode select
Selects whether the CPU clock frequency = input clock frequency x1 (Bypass), x6,
or x12.
For more details on the CLKMODE pins and the PLL multiply factors, see the Clock
PLL section of this data sheet.
PLL voltage supply
CLKMODE0
AA2
I
IPD
PLLV
V6
A#
JTAG EMULATION
TMS
E15
I
IPU
JTAG test-port mode select
TDO
B18
O/Z
IPU
JTAG test-port data out
TDI
A18
I
IPU
JTAG test-port data in
TCK
A16
I
IPU
JTAG test-port clock
TRST
D14
I
IPD
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG
compatibility statement portion of this data sheet.
EMU11
D17
I/O/Z
IPU
Emulation clock 1. Reserved for future use, leave unconnected.
EMU10
C17
I/O/Z
IPU
Emulation clock 0. Reserved for future use, leave unconnected.
EMU9
B17
I/O/Z
IPU
Emulation pin 9. Reserved for future use, leave unconnected.
EMU8
D16
I/O/Z
IPU
Emulation pin 8. Reserved for future use, leave unconnected.
EMU7
A17
I/O/Z
IPU
Emulation pin 7. Reserved for future use, leave unconnected.
EMU6
C16
I/O/Z
IPU
Emulation pin 6. Reserved for future use, leave unconnected.
EMU5
B16
I/O/Z
IPU
Emulation pin 5. Reserved for future use, leave unconnected.
EMU4
D15
I/O/Z
IPU
Emulation pin 4. Reserved for future use, leave unconnected.
EMU3
C15
I/O/Z
IPU
Emulation pin 3. Reserved for future use, leave unconnected.
EMU2
B15
I/O/Z
IPU
Emulation pin 2. Reserved for future use, leave unconnected.
Emulation pin 1||
Emulation pin 0||
EMU1
C14
I/O/Z
IPU
EMU0
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin.
#A = Analog signal (PLL Filter)
||The EMU0 and EMU1 pins are internally pulled up with 30-k
resistors; therefore, for emulation and normal operation, no external
pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-k
resistor.
A15
I/O/Z
IPU
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