參數(shù)資料
型號： TMX320C6412GNZ
廠商： Texas Instruments, Inc.
英文描述： Signal Processor
中文描述： 信號處理器
文件頁數(shù)： 67/159頁
文件大?。?/td> 1989K
代理商： TMX320C6412GNZ
Terminal Functions
67
April 2003 Revised June 2004
SPRS219D
Table 210. Terminal Functions (Continued)
SIGNAL
DESCRIPTION
IPU
TYPE
NAME
IPD/
GDK/
GNZ
HOST-PORT INTERFACE (HPI) OR PERIPHERAL COMPONENT INTERCONNECT (PCI) OR EMAC (CONTINUED)
HD31/AD31/MRCLK§
G1
HD30/AD30/MCRS§
H3
HD29/AD29/MRXER§
G2
HD28/AD28/MRXDV§
J4
HD27/AD27/MRXD3§
H2
HD26/AD26/MRXD2§
J3
HD25/AD25/MRXD1§
J1
HD24/AD24/MRXD0§
K4
HD23/AD23§
K1
HD22/AD22/MTCLK§
L4
HD21/AD21/MCOL§
K2
HD20/AD20/MTXEN§
L3
HD19/AD19/MTXD3§
L2
HD18/AD18/MTXD2§
M4
HD17/AD17/MTXD1§
M2
HD16/AD16/MTXD0§
M3
HD15/AD15§
T3
HD14/AD14§
U1
HD13/AD13§
U3
HD12/AD12§
U2
HD11/AD11§
U4
HD10/AD10§
V1
HD9/AD9§
V3
HD8/AD8§
V2
HD7/AD7§
W2
HD6/AD6§
W4
HD5/AD5§
Y1
HD4/AD4§
W3
HD3/AD3§
Y2
HD2/AD2§
Y4
HD1/AD1§
AA1
HD0/AD0§
Y3
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin.
#A = Analog signal (PLL Filter)
||The EMU0 and EMU1 pins are internally pulled up with 30-k
resistors; therefore, for emulation and normal operation, no external
pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-k
resistor.
Host-port data (
I/O/Z
) [default] or PCI data-address bus (
I/O/Z
) or EMAC
transmit/receive or control pins
As HPI data bus (PCI_EN pin = 0)
Used for transfer of data, address, and control
Host-Port bus width user-configurable at device reset via a 10-k
resistor pullup/
pulldown resistor on the HD5 pin:
HD5 pin = 0: HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins
are reserved pins in the high-impedance state.)
I/O/Z
HD5 pin = 1: HPI operates as an HPI32.
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
As PCI data-address bus (PCI_EN pin = 1)
Used for transfer of data and address
For superset devices like C6412, the HD31/AD31 through HD16/AD16 pins can also
function as EMAC transmit/receive or control pins (when PCI_EN pin = 0; MAC_EN
pin = 1). For more details on the EMAC pin functions, see the
Ethernet MAC (EMAC)
peripheral
section of this table and for more details on how to configure the EMAC pin,
see the device configuration section of this data sheet.
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