參數(shù)資料
型號： TMX320C6412GNZ
廠商： Texas Instruments, Inc.
英文描述： Signal Processor
中文描述： 信號處理器
文件頁數(shù)： 65/159頁
文件大?。?/td> 1989K
代理商： TMX320C6412GNZ
Terminal Functions
65
April 2003 Revised June 2004
SPRS219D
Table 210. Terminal Functions (Continued)
SIGNAL
DESCRIPTION
IPU
TYPE
NAME
IPD/
GDK/
GNZ
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS
RESET
P4
I
Device reset
NMI
B4
I
IPD
Nonmaskable interrupt, edge-driven (rising edge)
GP0[7]/EXT_INT7
E1
I/O/Z
IPU
The default after reset setting is GPIO enabled as input-only.
When these pins function as External Interrupts [by selecting the corresponding
interrupt enable register bit (IER.[7:4])], they are edge-driven and the polarity can
be independently selected via the External Interrupt Polarity Register bits
(EXTPOL.[3:0]).
GP0[6]/EXT_INT6
F2
I/O/Z
IPU
General-purpose input/output (GPIO) pins (
I/O/Z
) or external interrupts (
input only
).
GP0[5]/EXT_INT5
F3
I/O/Z
IPU
GP0[4]/EXT_INT4
F4
I/O/Z
IPU
GP0[15]/PRST§
G3
General-purpose input/output (GP0) 15 pin (
I/O/Z
) or PCI reset (
I
). No function at
default.
GP0[14]/PCLK§
GP0[13]/PINTA§
GP0[12]/PGNT§
GP0[11]/PREQ§
GP0[10]/PCBE3§
GP0[9]/PIDSEL§
C1
GP0 14 pin (
I/O/Z
) or PCI clock (
I
). No function at default.
GP0 13 pin (
I/O/Z
) or PCI interrupt A (
O/Z
). No function at default.
GP0 12 pin (
I/O/Z
) or PCI bus grant (
I
). No function at default.
GP0 11 pin (
I/O/Z
) or PCI bus request (
O/Z
). No function at default.
GP0 10 pin (
I/O/Z
) or PCI command/byte enable 3 (
I/O/Z
). No function at default.
GP0 9 pin (
I/O/Z
) or PCI initialization device select (
I
). No function at default.
GP0 3 pin (
I/O/Z
) and PCI EEPROM Auto-Initialization (EEAI).
If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must
not
be pulled up.
0
PCI auto-initialization through EEPROM is disabled (default).
1
PCI auto-initialization through EEPROM is enabled.
G4
H4
F1
I/O/Z
J2
K3
GP0[3]/PCIEEAI
L5
IPD
GP0[0]
M5
I/O/Z
IPD
GP0 0 pin (
I/O/Z
) [default].
The general-purpose 0 pin (GP0[0]) (
I/O/Z
) can be programmed as GPIO 0 (
input
only
) [default] or as GP0[0] (
output only
) pin or output as a general-purpose interrupt
(GP0INT) signal (
output only
). This pin
must
remain low during device reset.
This pin can be programmed as a GP0 8 pin (
I/O/Z
) or PCI frequency selection (PCI66).
If the PCI peripheral is enabled (PCI_EN pin = 1), then:
0
PCI operates at 66 MHz (default).
1
PCI operates at 33 MHz.
The -500 device supports PCI at 33 MHz only. For proper -500 device operation when
the PCI peripheral is enabled (PCI_EN = 1), this pin
must
be pulled up with a 1-k
resistor at device reset.
If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must
not
be pulled up.
GP0[8]/PCI66§
AD1
I/O/Z
IPD
CLKOUT6/GP0[2]§
C6
I/O/Z
IPD
Clock output at 1/6 of the device speed (
O/Z
) [default] or this pin can be programmed as
a GP0 2 pin (
I/O/Z
).
CLKOUT4/GP0[1]§
D6
I/O/Z
IPD
Clock output at 1/4 of the device speed (
O/Z
) [default] or this pin can be programmed as
a GP0 1 pin (
I/O/Z
).
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin.
#A = Analog signal (PLL Filter)
||The EMU0 and EMU1 pins are internally pulled up with 30-k
resistors; therefore, for emulation and normal operation, no external
pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-k
resistor.
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