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參數(shù)資料
| 型號(hào)： | TMX320C6412GNZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Signal Processor |
| 中文描述： | 信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 5/159頁(yè) |
| 文件大?。?/td> | 1989K |
| 代理商： | TMX320C6412GNZ |
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Revision History
5
April 2003 Revised June 2004
SPRS219D
PAGE(s)
NO.
ADDS/CHANGES/DELETES
105
Recommended Operating Conditions:
Added the VOS, Maximum voltage during overshoot/undershoot specification and parameter MIN/MAX values
Added associated overshoot/undershoot footnote
106
Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature:
Moved all the ICDD, Core supply current parameter values
from
“MAX”
to
“TYP”
Moved all the IDDD, I/O supply current parameter values
from
“MAX”
to
“TYP”
Updated/changed “The actual current draw is highly application-dependent ...” footnote “TBD” with “The
TMS320C6412
Power Consumption Summary
application report (literature number SPRA967)” reference
109
Input and Output Clocks section:
Timing Requirements for CLKIN for 500 Devices table:
Timing Requirements for CLKIN for 600 Devices table:
Added parameter No. 5, tJ(CLKIN), Period jitter, CLKIN
Changed the “PLL MODE x6” and “PLL MODE x12” MIN values of parameter #2 “tw(CLKINH),
Pulse duration, CLKIN high”
from
“0.4C”
to
“0.45C” ns
Changed the “PLL MODE x6” and “PLL MODE x12” MIN values of parameter #3 “tw(CLKINL),
Pulse duration, CLKIN low”
from
“0.4C”
to
“0.45C” ns
Updated/changed Figure 45, CLKIN Timing, to include jitter parameter #5
110
Input and Output Clocks section:
Switching Characteristics Over Recommended Operating Conditions for CLKOUT4 table:
Deleted parameter No. 1, tJ(CKO4), Cycle-to-cycle jitter, CLKOUT4” and renumbered remaining parameters
Updated/changed Figure 46, CLKOUT4 Timing
110
Input and Output Clocks section:
Switching Characteristics Over Recommended Operating Conditions for CLKOUT6 table:
Deleted parameter No. 1, “tJ(CKO6), Cycle-to-cycle jitter, CLKOUT6” and renumbered remaining parameters
Updated/changed Figure 47, CLKOUT6 Timing
111
Input and Output Clocks section:
Timing Requirements for AECLKIN for EMIFA table:
Changed MAX value of parameter #4 “tt(EKI),
Transition time, AECLKIN”
from
“2”
to
“3” ns
Added parameter No. 5, tJ(EKI), Period jitter, AECLKIN
Added associated “E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA” footnote
Added “Minimum AECLKIN cycle times
must
be met, even when AECLKIN is generated by an internal clock source.” to the
“Minimum AECLKIN times are based on internal logic speed ...” footnote
Updated/changed Figure 48, AECLKIN Timing for EMIFA, to include jitter parameter #5
111
Input and Output Clocks section:
Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for the EMIFA Module table:
Deleted parameter No. 1, “tJ(EKO1), Cycle-to-cycle jitter, AECLKOUT1” and renumbered remaining parameters
Updated/changed Figure 49, AECLKOUT1 Timing for EMIFA Module
112
Input and Output Clocks section:
Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the EMIFA Module table:
Changed the MIN value of parameter No. 5, td(EKIH-EKO2H)
from
3 ns
to
1 ns
Changed the MIN value of parameter No. 6, td(EKIH-EKO2L)
from
3 ns
to
1 ns
Deleted parameter No. 1, “tJ(EKO2), Cycle-to-cycle jitter, AECLKOUT2” and renumbered remaining parameters
Updated/changed Figure 410, AECLKOUT2 Timing for EMIFA Module
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