參數(shù)資料
型號： TMX320C6412GNZ
廠商： Texas Instruments, Inc.
英文描述： Signal Processor
中文描述： 信號處理器
文件頁數(shù)： 111/159頁
文件大?。?/td> 1989K
代理商： TMX320C6412GNZ
Input and Output Clocks
111
April 2003 Revised June 2004
SPRS219D
Table 46. Timing Requirements for AECLKIN for EMIFA
§
(see Figure 48)
NO.
500
600
UNIT
MIN
6
MAX
1
tc(EKI)
tw(EKIH)
tw(EKIL)
tt(EKI)
tJ(EKI)
Cycle time, AECLKIN
16P
ns
2
Pulse duration, AECLKIN high
2.7
ns
3
Pulse duration, AECLKIN low
2.7
ns
4
Transition time, AECLKIN
3
ns
5
Period jitter, AECLKIN
0.02E
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
§E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
Minimum AECLKIN cycle times
must
be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times are based
on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. On the 600 devices, 133-MHz
operation is achievable if the requirements of the EMIF Device Speed section are met. On the 500 devices, 100-MHz operation is achievable
if the requirements of the EMIF Device Speed section are met.
AECLKIN
2
3
4
4
5
1
Figure 48. AECLKIN Timing for EMIFA
Table 47. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for the
EMIFA Module
#||
(see Figure 49)
NO.
PARAMETER
500
600
UNIT
MIN
MAX
1
tw(EKO1H)
tw(EKO1L)
tt(EKO1)
td(EKIH-EKO1H)
td(EKIL-EKO1L)
The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
#E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
||EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.
This cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
Pulse duration, AECLKOUT1 high
EH 0.7
EH + 0.7
ns
2
Pulse duration, AECLKOUT1 low
EL 0.7
EL + 0.7
ns
3
Transition time, AECLKOUT1
1
ns
4
Delay time, AECLKIN high to AECLKOUT1 high
1
8
ns
5
Delay time, AECLKIN low to AECLKOUT1 low
1
8
ns
4
5
1
2
AECLKIN
AECLKOUT1
3
3
Figure 49. AECLKOUT1 Timing for EMIFA Module
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