參數(shù)資料
型號: TMX320C6412GNZ
廠商: Texas Instruments, Inc.
英文描述: Signal Processor
中文描述: 信號處理器
文件頁數(shù): 60/159頁
文件大?。?/td> 1989K
代理商: TMX320C6412GNZ
Device Configurations
60
April 2003 Revised June 2004
SPRS219D
Table 29. C6412 Device Multiplexed Pins
MULTIPLEXED PINS
NAME
DEFAULT
FUNCTION
DEFAULT
SETTING
DESCRIPTION
NO.
CLKOUT4/GP0[1]
D6
CLKOUT4
GP1EN = 0 (disabled)
These pins are software-configurable. To use these pins as
GPIO pins, the GPxEN bits in the GPIO Enable Register and
the GPxDIR bits in the GPIO Direction Register must be
properly configured.
GPxEN = 1:
GPx pin enabled
GPxDIR = 0:
GPx pin is an input
GPxDIR = 1:
GPx pin is an output
CLKOUT6/GP0[2]
C6
CLKOUT6
GP2EN = 0 (disabled)
GP0[3]/PCIEEAI
L5
PCIEEAI
GP3EN = 0 (disabled)
To use the PCI autoinitialization EEPROM (PCIEEAI) the
PCI needs to be enabled (PCI_EN = 1):
0
PCI auto-init through EEPROM disabled (default).
1
PCI auto-init through EEPROM is enabled.
To use GP0[3] as a GPIO pin, the PCI needs to be disabled
(PCI_EN = 0), the GP3EN bits in the GPIO Enable Register
and the GP3DIR bits in the GPIO Direction Register must be
properly configured.
GP3EN = 1:
GP3 pin enabled
GP3DIR = 0:
GP3 pin is an input
GP3DIR = 1:
GP3 pin is an output
To use GP0[8] as a GPIO pin, the PCI needs to be disabled
(PCI_EN = 0), the GPxEN bits in the GPIO Enable Register
and the GPxDIR bits in the GPIO Direction Register must be
properly configured.
GP8EN = 1:
GP8 pin enabled
GP8DIR = 0:
GP8 pin is an input
GP8DIR = 1:
GP8 pin is an output
To use the PCI66 pin function, which changes the PCI
operating frequency selection, the PCI needs to be enabled
(PCI_EN = 1):
0
PCI operates at 66 MHz (default).
1
PCI operates at 33 MHz.
GP0[8]/PCI66
AD1
PCI66
GP8EN = 0 (disabled)
MAC_EN = 0 (disabled)
The -500 device supports PCI at 33 MHz only. For proper
-500 device operation when the PCI peripheral is enabled
(PCI_EN = 1), this pin
must
be pulled up with a 1-k
resistor
at device reset.
If the PCI peripheral is disabled (PCI_EN pin = 0), this pin
must
not
be pulled up.
GP0[9]/PIDSEL
K3
GP0[10]/PCBE3
J2
To use GP0[15:9] as GPIO pins, the PCI needs to be disabled
(PCI_EN = 0), the GPxEN bits in the GPIO Enable Register
and the GPxDIR bits in the GPIO Direction Register must be
GPxEN = 1:
GPx pin enabled
GPxDIR = 0:
GPx pin is an input
GPxDIR = 1:
GPx pin is an output
GP0[11]/PREQ
F1
GPxEN = 0 (disabled)
PCI_EN = 0 (disabled)
GP0[12]/PGNT
H4
None
GP0[13]/PINTA
G4
properly configured.
GP0[14]/PCLK
C1
GP0[15]/PRST
All other standalone PCI pins are tied-off internally (pins in Hi-Z) when the peripheral is disabled [PCI_EN = 0].
For the HD[31:0]/AD[31:0] multiplexed pins pin numbers, see the
Terminal Functions
table.
G3
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