參數(shù)資料
型號(hào)： TMX320C6412GNZ
廠商： Texas Instruments, Inc.
英文描述： Signal Processor
中文描述： 信號(hào)處理器
文件頁數(shù)： 73/159頁
文件大?。?/td> 1989K
代理商： TMX320C6412GNZ
Terminal Functions
73
April 2003 Revised June 2004
SPRS219D
Table 210. Terminal Functions (Continued)
SIGNAL
DESCRIPTION
IPU
TYPE
NAME
IPD/
GDK/
GNZ
TIMER 0
TOUT0/MAC_EN
C5
O/Z
IPD
Timer 0 output (
O/Z
) or MAC enable select bit (
I
)
MAC enable pin. This pin and the MAC_EN pin control the selection (enable/disable) of
the HPI, EMAC, MDIO, and GP0[15:9], or PCI peripherals. The pins work in conjunction
to enable/disable these peripherals (for more details, see the Device Configurations
section of this data sheet).
For more details, see the Device Configurations section of this data sheet.
TINP0
A4
I
IPD
Timer 0 or general-purpose input
INTER-INTEGRATED CIRCUIT 0 (I2C0)
SCL0
E4
I/O/Z
—
I2C0 clock.
SDA0
D3
I/O/Z
—
I2C0 data.
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKR1
AD8
I/O/Z
IPD
McBSP1 receive clock (
I/O/Z
)
FSR1
AC7
I/O/Z
IPD
McBSP1 receive frame sync (
I/O/Z
)
DR1
AD7
I
IPD
McBSP1 receive data (
I
)
CLKS1
AE7
I
IPD
McBSP1 external clock source (
I
) (as opposed to internal)
DX1
AC6
I/O/Z
IPD
McBSP1 transmit data (
O/Z
)
FSX1
AD6
I/O/Z
IPD
McBSP1 transmit frame sync (
I/O/Z
)
CLKX1
AE6
I/O/Z
IPD
McBSP1 transmit clock (
I/O/Z
)
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKR0
AE15
I/O/Z
IPD
McBSP0 receive clock (
I/O/Z
)
FSR0
AB16
I/O/Z
IPD
McBSP0 receive frame sync (
I/O/Z
)
DR0
AC16
I
IPU
McBSP0 receive data (
I
)
CLKS0
AD16
I
IPD
McBSP0 external clock source (
I
) (as opposed to internal)
DX0
AE16
O/Z
IPU
McBSP0 transmit data (
O/Z
)
FSX0
AF16
I/O/Z
IPD
McBSP0 transmit frame sync (
I/O/Z
)
CLKX0
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin.
#A = Analog signal (PLL Filter)
||The EMU0 and EMU1 pins are internally pulled up with 30-k
resistors; therefore, for emulation and normal operation, no external
pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-k
resistor.
AF17
I/O/Z
IPD
McBSP0 transmit clock (
I/O/Z
)
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