參數(shù)資料
型號： TMX320C6412GNZ
廠商： Texas Instruments, Inc.
英文描述： Signal Processor
中文描述： 信號處理器
文件頁數(shù)： 133/159頁
文件大?。?/td> 1989K
代理商： TMX320C6412GNZ
Host-Port Interface (HPI) Timing
133
April 2003 Revised June 2004
SPRS219D
13
Host-Port Interface (HPI) Timing
Table 131. Timing Requirements for Host-Port Interface Cycles
(see Figure 131 through Figure 138)
NO.
500
600
UNIT
MIN
5
MAX
1
tsu(SELV-HSTBL)
th(HSTBL-SELV)
tw(HSTBL)
tw(HSTBH)
tsu(SELV-HASL)
th(HASL-SELV)
tsu(HDV-HSTBH)
th(HSTBH-HDV)
Setup time, select signals§ valid before HSTROBE low
Hold time, select signals§ valid after HSTROBE low
ns
2
2.4
4P
ns
3
Pulse duration, HSTROBE low
ns
4
Pulse duration, HSTROBE high between consecutive accesses
Setup time, select signals§ valid before HAS low
Hold time, select signals§ valid after HAS low
4P
ns
10
5
ns
11
2
ns
12
Setup time, host data valid before HSTROBE high
5
ns
13
Hold time, host data valid after HSTROBE high
2.8
ns
14
th(HRDYL-HSTBL)
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not complete
properly.
2
ns
18
tsu(HASL-HSTBL)
th(HSTBL-HASL)
Setup time, HAS low before HSTROBE low
2
ns
19
Hold time, HAS low after HSTROBE low
2.1
ns
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
§Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.
Select the parameter value of 4P or 12.5 ns, whichever is larger.
Table 132. Switching Characteristics Over Recommended Operating Conditions During Host-Port
Interface Cycles
(see Figure 131 through Figure 138)
NO.
PARAMETER
500
600
UNIT
MIN
MAX
6
td(HSTBL-HRDYH)
td(HSTBL-HDLZ)
td(HDV-HRDYL)
toh(HSTBH-HDV)
td(HSTBH-HDHZ)
td(HSTBL-HDV)
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
#This parameter is used during HPID reads and writes. For reads, at the beginning of a word transfer (HPI32) or the first half-word transfer (HPI16)
on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until
the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is
full.
Delay time, HSTROBE low to HRDY high#
1.3
4P + 8
ns
7
Delay time, HSTROBE low to HD low impedance for an HPI read
2
ns
8
Delay time, HD valid to HRDY low
3
ns
9
Output hold time, HD valid after HSTROBE high
1.5
ns
15
Delay time, HSTROBE high to HD high impedance
12
ns
16
Delay time, HSTROBE low to HD valid (HPI16 mode, 2nd half-word only)
4P + 8
ns
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