參數(shù)資料
型號: TMX320C6412GNZ
廠商: Texas Instruments, Inc.
英文描述: Signal Processor
中文描述: 信號處理器
文件頁數(shù): 138/159頁
文件大?。?/td> 1989K
代理商: TMX320C6412GNZ
Peripheral Component Interconnect (PCI) Timing
138
April 2003 Revised June 2004
SPRS219D
14
Peripheral Component Interconnect (PCI) Timing
Table 141. Timing Requirements for PCLK
(see Figure 141)
NO.
500 [33 MHz]
MIN
30 (or 4P§)
600 [66 MHz]
MIN
15 (or 4P§)
UNIT
MAX
MAX
1
tc(PCLK)
tw(PCLKH)
tw(PCLKL)
tsr(PCLK)
Cycle time, PCLK
ns
2
Pulse duration, PCLK high
11
6
ns
3
Pulse duration, PCLK low
v/
t slew rate, PCLK
11
6
ns
4
1
4
1.5
4
V/ns
For 3.3-V operation, the reference points for the rise and fall transitions are measured at VILP MAX and VIHP MIN.
P = 1/CPU clock frequency in ns. For example when running parts at 600 MHz,
use P = 1.67 ns.
§Select the parameter value, whichever is larger.
PCLK
1
2
3
4
4
0.4 DVDD V MIN
Peak to Peak for
3.3V signaling
Figure 141. PCLK Timing
Table 142. Timing Requirements for PCI Reset (see Figure 142)
NO.
500
600
UNIT
MIN
MAX
1
tw(PRST)
tsu(PCLKA-PRSTH)
Pulse duration, PRST
1
ms
μ
s
2
Setup time, PCLK active before PRST high
100
PRST
PCLK
2
1
Figure 142. PCI Reset (PRST) Timing
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