參數(shù)資料
型號： TMX320C6412GNZ
廠商： Texas Instruments, Inc.
英文描述： Signal Processor
中文描述： 信號處理器
文件頁數(shù)： 148/159頁
文件大?。?/td> 1989K
代理商： TMX320C6412GNZ
Multichannel Buffered Serial Port (McBSP) Timing
148
April 2003 Revised June 2004
SPRS219D
Table 1510. Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 11b, CLKXP = 1
(see Figure 156)
NO.
500
600
UNIT
MASTER
MIN
SLAVE
MIN
MAX
MAX
4
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
12
2 12P
ns
5
Hold time, DR valid after CLKX high
4
5 + 24P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 1511. Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
(see Figure 156)
NO.
PARAMETER
500
600
UNIT
MASTER§
SLAVE
MIN
MAX
MIN
MAX
1
th(CKXH-FXL)
td(FXL-CKXL)
td(CKXH-DXV)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low#
H 2
H + 3
ns
2
T 2.5
T + 1.5
ns
3
Delay time, CLKX high to DX valid
2
4
12P + 3
20P + 17
ns
6
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX high
2
4
12P + 3
20P + 17
ns
7
td(FXL-DXV)
Delay time, FSX low to DX valid
L 2
L + 4
8P + 2
16P + 17
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S =
Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T =
CLKX period = (1 + CLKGDV) * S
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
#FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
5
4
3
7
6
2
1
CLKX
FSX
DX
DR
Figure 156. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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