
Device Configurations
56
April 2003 Revised June 2004
SPRS219D
Read Accesses
31
1
0
Reserved
LOCKSTAT
R-0
R-1
Write Accesses
31
0
LOCK
W-0
Legend:
R = Read only; R/W = Read/Write; -n = value after reset
Figure 23. PCFGLOCK Register Diagram [Address Location: 0x01B3 F018] Read/Write Accesses
Table 25. PCFGLOCK Register Selection Bit Descriptions Read Accesses
BIT
NAME
DESCRIPTION
31:1
Reserved
Reserved. Read-only, writes have no effect.
0
LOCKSTAT
Lock status bit.
Determines whether the PERCFG register is locked or unlocked.
0
=
Unlocked, read accesses to the PERCFG register allowed.
1
=
Locked, write accesses to the PERCFG register do
not
modify the register state [default].
Reads are unaffected by Lock Status.
Table 26. PCFGLOCK Register Selection Bit Descriptions Write Accesses
BIT
NAME
DESCRIPTION
31:0
LOCK
Lock bits.
0x10C0010C = Unlocks PERCFG register accesses.
Any write to the PERCFG register will automatically relock the register. In order to avoid the unnecessary
overhead of multiple unlock/enable sequences, all peripherals should be enabled with a single write to the
PERCFG register with the necessary enable bits set.
Prior to waiting 128 CPU cycles, the PERCFG register should be read. There is no direct correlation between
the CPU issuing a write to the PERCFG register and the write actually occurring. Reading the PERCFG
register after the write is issued forces the CPU to wait for the write to the PERCFG register to occur.
Once a peripheral is enabled, the DSP (or other peripherals such as the HPI) must wait a minimum of 128 CPU
cycles before accessing the enabled peripheral. The user
must
ensure that no accesses are performed to a
peripheral while it is disabled.