參數(shù)資料
型號： TMX320C6412GNZ
廠商： Texas Instruments, Inc.
英文描述： Signal Processor
中文描述： 信號處理器
文件頁數(shù)： 19/159頁
文件大?。?/td> 1989K
代理商： TMX320C6412GNZ
Features
19
April 2003 Revised June 2004
SPRS219D
1
Features
High-Performance Fixed-Point Digital
Signal Processor (TMS320C6412)
2-, 1.67-ns Instruction Cycle Time
500-, 600-MHz Clock Rate
Eight 32-Bit Instructions/Cycle
4000, 4800 MIPS
Fully Software-Compatible With C64x
VelociTI.2
Extensions to VelociTI
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x
DSP Core
Eight Highly Independent Functional
Units With VelociTI.2
Extensions:
Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad
8-Bit Arithmetic per Clock Cycle
Two Multipliers Support
Four 16 x 16-Bit Multiplies
(32-Bit Results) per Clock Cycle or
Eight 8 x 8-Bit Multiplies
(16-Bit Results) per Clock Cycle
Load-Store Architecture With
Non-Aligned Support
64 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
Instruction Set Features
Byte-Addressable (8-/16-/32-/64-Bit Data)
8-Bit Overflow Protection
Bit-Field Extract, Set, Clear
Normalization, Saturation, Bit-Counting
VelociTI.2
Increased Orthogonality
L1/L2 Memory Architecture
128K-Bit (16K-Byte) L1P Program Cache
(Direct Mapped)
128K-Bit (16K-Byte) L1D Data Cache
(2-Way Set-Associative)
2M-Bit (256K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible RAM/Cache Allocation)
Endianess: Little Endian, Big Endian
64-Bit External Memory Interface (EMIF)
Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
Synchronous Memories (SDRAM,
SBSRAM, ZBT SRAM, and FIFO)
1024M-Byte Total Addressable External
Memory Space
Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
10/100 Mb/s Ethernet MAC (EMAC)
IEEE 802.3 Compliant
Media Independent Interface (MII)
8 Independent Transmit (TX) Channels
and 1 Receive (RX) Channel
Management Data Input/Output (MDIO)
Host-Port Interface (HPI) [32-/16-Bit]
32-Bit/66-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
Conforms to PCI Specification 2.2
Inter-Integrated Circuit (I
2
C) Bus
Two Multichannel Buffered Serial Ports
Three 32-Bit General-Purpose Timers
Sixteen General-Purpose I/O (GPIO) Pins
Flexible PLL Clock Generator
IEEE-1149.1 (JTAG
)
Boundary-Scan-Compatible
548-Pin Ball Grid Array (BGA) Package
(GDK Suffix), 0.8-mm Ball Pitch
548-Pin Ball Grid Array (BGA) Package
(GNZ Suffix), 1.0-mm Ball Pitch
0.13-
μ
m/6-Level Cu Metal Process (CMOS)
3.3-V I/Os, 1.2-V Internal (-500)
3.3-V I/Os, 1.4-V Internal (A-500, -600)
C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
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