
Peripheral Register Descriptions
41
April 2003 Revised June 2004
SPRS219D
Table 116. Timer 0 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
0194 0000
CTL0
Timer 0 control register
Determines the operating mode of the timer, monitors the
timer status, and controls the function of the TOUT pin.
0194 0004
PRD0
Timer 0 period register
Contains the number of timer input clock cycles to count.
This number controls the TSTAT signal frequency.
0194 0008
CNT0
Timer 0 counter register
Contains the current value of the incrementing counter.
0194 000C 0197 FFFF
Reserved
Table 117. Timer 1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
0198 0000
CTL1
Timer 1 control register
Determines the operating mode of the timer, monitors the
timer status, and controls the function of the TOUT pin.
0198 0004
PRD1
Timer 1 period register
Contains the number of timer input clock cycles to count.
This number controls the TSTAT signal frequency.
0198 0008
CNT1
Timer 1 counter register
Contains the current value of the incrementing counter.
0198 000C 019B FFFF
Reserved
Table 118. Timer 2 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
01AC 0000
CTL2
Timer 2 control register
Determines the operating mode of the timer, monitors the
timer status.
01AC 0004
PRD2
Timer 2 period register
Contains the number of timer input clock cycles to count.
This number controls the TSTAT signal frequency.
01AC 0008
CNT2
Timer 2 counter register
Contains the current value of the incrementing counter.
01AC 000C 01AF FFFF
Reserved
Table 119. HPI Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
HPID
HPI data register
Host read/write access only
0188 0000
HPIC
HPI control register
HPIC has both Host/CPU read/write access
0188 0004
HPIA
(HPIAW)
HPIA
(HPIAR)
HPI address register
(Write)
HPI address register
(Read)
HPIA has both Host/CPU read/write access
0188 0008
0188 000C 0189 FFFF
Reserved
018A 0000
HPI_TRCTL
HPI transfer request control
register
018A 0004 018B FFFF
Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR independently.
Reserved