參數(shù)資料
型號： TMX320C6412GNZ
廠商： Texas Instruments, Inc.
英文描述： Signal Processor
中文描述： 信號處理器
文件頁數(shù)： 74/159頁
文件大?。?/td> 1989K
代理商： TMX320C6412GNZ
Terminal Functions
74
April 2003 Revised June 2004
SPRS219D
Table 210. Terminal Functions (Continued)
SIGNAL
DESCRIPTION
IPU
TYPE
NAME
IPD/
GDK/
GNZ
ETHERNET MAC (EMAC)
HD31/AD31/MRCLK§
HD30/AD30/MCRS§
HD29/AD29/MRXER§
HD28/AD28/MRXDV§
HD27/AD27/MRXD3§
HD26/AD26/MRXD2§
HD25/AD25/MRXD1§
HD24/AD24/MRXD0§
HD22/AD22/MTCLK§
HD21/AD21/MCOL§
HD20/AD20/MTXEN§
HD19/AD19/MTXD3§
HD18/AD18/MTXD2§
HD17/AD17/MTXD1§
HD16/AD16/MTXD0§
G1
I
EMAC Media Independent I/F (MII) data, clocks, and control pins for Transmit/Receive.
MII transmit clock (MTCLK),
Transmit clock source from the attached PHY.
MII transmit data (MTXD[3:0]),
Transmit data nibble synchronous with transmit clock (MTCLK).
MII transmit enable (MTXEN),
This signal indicates a valid transmit data on the transmit data pins (MTDX[3:0]).
Assertion of this signal during half-duplex operation indicates network collision.
During full-duplex operation, transmission of new frames will not begin if this pin is
MII carrier sense (MCRS)
Indicates a frame carrier signal is being received.
MII receive data (MRXD[3:0]),
Receive data nibble synchronous with receive clock (MRCLK).
MII receive clock (MRCLK),
Receive clock source from the attached PHY.
MII receive data valid (MRXDV),
This signal indicates a valid data nibble on the receive data pins (MRDX[3:0]).
and MII receive error (MRXER),
Indicates reception of a coding error on the receive data.
H3
I
G2
I
J4
I
H2
I
J3
I
J1
I
MII collision sense (MCOL)
K4
I
L4
I
asserted.
K2
I
L3
O/Z
L2
O/Z
M4
O/Z
M2
O/Z
M3
O/Z
RESERVED FOR TEST
Reserved. This pin must be connected directly to CVDD for proper device operation.
Reserved. This pin must be connected directly to DVDD for proper device operation.
RSV
H7
A
—
R6
A
—
A7
A9
RSV
A10
Reserved. This pin must be connected directly to CVDD for proper device operation.
A11
A13
B8
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin.
#A = Analog signal (PLL Filter)
||The EMU0 and EMU1 pins are internally pulled up with 30-k
resistors; therefore, for emulation and normal operation, no external
pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-k
resistor.
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