- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385002 > TMX320C6412GNZ (Texas Instruments, Inc.) Signal Processor PDF資料下載
參數(shù)資料
| 型號(hào)： | TMX320C6412GNZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Signal Processor |
| 中文描述： | 信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 6/159頁(yè) |
| 文件大小： | 1989K |
| 代理商： | TMX320C6412GNZ |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)當(dāng)前第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)
Revision History
6
April 2003 Revised June 2004
SPRS219D
PAGE(s)
NO.
ADDS/CHANGES/DELETES
113
Asynchronous Memory Timing section:
Timing Requirements for Asynchronous Memory Cycles for EMIFA Module table:
Deleted “The AARDY signal is recognized in the cycle for which the setup and hold time is met.” from the AARDY signal
footnote
Added “The AARDY signal is
only
recognized two cycles before the end of the programmed strobe time and while AARDY is
low, the strobe time is extended cycle-by-cycle. When AARDY is recognized low, the end of the strobe time is two cycles
after AARDY is recognized high.” to the AARDY footnote
126
HOLD/HOLDA Timing section:
Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module table:
Changed parameter NO. 3
from
“toh(HOLDAL-HOLDL)”
to
“th(HOLDAL-HOLDL)”
128129
Reset Timing section:
Timing Requirements for Reset table:
Changed the MIN value of parameter No. 17, th(boot)
from
“4E or 4C” ns
to
“4P” ns
Added the associated “P note” footnote
Added parameter NO. 18, “td(PCLKRSTH) Delay time, PCLK active to RESET high” with a MIN value of “32N” ns
Changed parameter NO. 18 description
from
“td(PCLKRSTH) Delay time, PCLK active to RESET high”
to
“tsu(PCLK-RSTH),
Setup time, PCLK active before RESET high”
Added associated footnote to identify “N” and restraints
Switching Characteristics Over Recommended Operating Conditions During Reset table:
Updated footnote symbols
Figure 101, Reset Timing:
Updated figure to include the PCLK signal and parameter 18
Added “MAC_EN” to the “If AEA[22:19], LENDIAN, PCIEEAI, and HD5/AD5 pins ...” footnote
Added/Updated the “Boot and Device Configurations Inputs (during reset) include: ...” footnote
133
Host-Port Interface (HPI) Timing section:
Switching Characteristics Over Recommended Operating Conditions During Host-Port Interface Cycles table:
Added “mode, 2nd half-word” to parameter NO. 16 “td(HSTBL-HDV), Delay time, HSTROBE low to HD valid (HPI16 only)”
141142
Multichannel Buffered Serial Port (McBSP) Timing section:
Timing Requirements for McBSP table:
Added the MIN value of “or 6.67” ns to No. 2, tc(CKRX) parameter
Changed/updated the associated footnote
Switching Characteristics Over Recommended Operating Conditions for McBSP table:
Added the MIN value of “or 6.67” ns to No. 2, tc(CKRX) parameter
Changed/updated the associated footnote
149
Ethernet Media Access Controller (EMAC) Timing section:
Timing Requirements for MRCLK table:
Deleted parameter No. 4, “tt(MRCLK), Transition time, MRCLK”
Deleted associated reference points for rise and fall transitions footnote
Updated/changed Figure 161, MRCLK Timing (EMAC Receive)
149
Ethernet Media Access Controller (EMAC) Timing section:
Timing Requirements for MTCLK table:
Deleted parameter No. 4, “tt(MTCLK), Transition time, MTCLK”
Deleted associated reference points for rise and fall transitions footnote
Updated/changed Figure 162, MTCLK Timing (EMAC Transmit)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMX320VC5421 | DIGITAL SIGNAL PROCESSOR |
| TMX320VC5509AGHH | TMS320VC5509A Fixed-Point Digital Signal Processor |
| TMX470R1A64PN | 16/32-Bit RISC Flash Microcontroller |
| TMXT504 | SAW BANDPASS FILTER |
| TN0104 | N-Channel Enhancement-Mode Vertical DMOS FET(擊穿電壓40V，低門限1.6V，N溝道增強(qiáng)型垂直DMOS結(jié)構(gòu)場(chǎng)效應(yīng)管) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMX320C6412ZDK | 制造商:Texas Instruments 功能描述: |
| TMX320C6413GTS | 制造商:Texas Instruments 功能描述: |
| TMX320C6413GTS400 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Fixed-Point Digital Signal Processors |
| TMX320C6413GTS500 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Fixed-Point Digital Signal Processors |
| TMX320C6413GTSA400 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Fixed-Point Digital Signal Processors |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。