參數(shù)資料
型號： TMX320C6412GNZ
廠商： Texas Instruments, Inc.
英文描述： Signal Processor
中文描述： 信號處理器
文件頁數(shù)： 21/159頁
文件大小： 1989K
代理商： TMX320C6412GNZ
Description
21
April 2003 Revised June 2004
SPRS219D
1.3
Description
The TMS320C64x
DSPs (including the TMS320C6412 device) are the highest-performance fixed-point
DSP generation in the TMS320C6000
DSP platform. The TMS320C6412 (C6412) device is based on the
second-generation high-performance, advanced VelociTI
very-long-instruction-word (VLIW) architecture
(VelociTI.2
) developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel
and multifunction applications. The C64x
is a code-compatible member of the C6000
DSP platform.
With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C6412
device offers cost-effective solutions to high-performance DSP programming challenges. The C6412 DSP
possesses the operational flexibility of high-speed controllers and the numerical capability of array
processors. The C64x
DSP core processor has 64 general-purpose registers of 32-bit word length and eight
highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)—
with VelociTI.2
extensions. The VelociTI.2
extensions in the eight functional units include new instructions
to accelerate the performance in applications and extend the parallelism of the VelociTI
architecture. The
C6412 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per
second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6412 DSP also has
application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other
C6000
DSP platform devices.
The C6412 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The
Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit
2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is
shared between program and data space. L2 memory can be configured as mapped memory, cache, or
combinations of the two. The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC); a management
data input/output (MDIO) module; an inter-integrated circuit (I2C) Bus module; two multichannel buffered
serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port
interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output
port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory
interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and
peripherals.
The ethernet media access controller (EMAC) provides an efficient interface between the C6412 DSP core
processor and the network. The C6412 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second
(Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS)
support. The C6412 EMAC makes use of a custom interface to the DSP core that allows efficient data
transmission and reception.
For more details on the EMAC, see the
TMS320C6000 DSP Ethernet Media
Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide
(literature
number SPRU628).
The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO
module transparently monitors its link state by reading the PHY status register. Link change events are stored
in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device
without continuously performing costly MDIO accesses. For more details on the MDIO port, see the
TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO)
Module Reference Guide
(literature number SPRU628).
The I2C0 port on the TMS320C6412 allows the DSP to easily control peripheral devices and communicate
with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to
communicate with serial peripheral interface (SPI) mode peripheral devices.
The C6412 has a complete set of development tools which includes: a new C compiler, an assembly optimizer
to simplify programming and scheduling, and a Windows
debugger interface for visibility into source code
execution.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
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