參數資料
型號： TMX320C6412GNZ
廠商： Texas Instruments, Inc.
英文描述： Signal Processor
中文描述： 信號處理器
文件頁數： 131/159頁
文件大?。?/td> 1989K
代理商： TMX320C6412GNZ
Inter-Integrated Circuits (I2C) Timing
131
April 2003 Revised June 2004
SPRS219D
12
Inter-Integrated Circuits (I2C) Timing
Table 121. Timing Requirements for I2C Timings
(see Figure 121)
500
600
NO.
STANDARD
MODE
FAST
MODE
UNIT
MIN
MAX
MIN
MAX
1
tc(SCL)
Cycle time, SCL
10
2.5
μ
s
2
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a repeated START
condition)
4.7
0.6
μ
s
3
th(SCLL-SDAL)
Hold time, SCL low after SDA low (for a START and a repeated
START condition)
4
0.6
μ
s
4
tw(SCLL)
tw(SCLH)
tsu(SDAV-SDLH)
th(SDA-SDLL)
tw(SDAH)
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
tsu(SCLH-SDAH)
tw(SP)
Cb#
Pulse duration, SCL low
4.7
1.3
μ
s
μ
s
ns
μ
s
μ
s
ns
5
Pulse duration, SCL high
4
0.6
6
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low (For I2C bus
devices)
Pulse duration, SDA high between STOP and START conditions
250
0§
100
0§
7
0.9
8
4.7
1.3
9
Rise time, SDA
1000
20 + 0.1Cb#
20 + 0.1Cb#
20 + 0.1Cb#
20 + 0.1Cb#
300
10
Rise time, SCL
1000
300
ns
11
Fall time, SDA
300
300
ns
12
Fall time, SCL
300
300
ns
μ
s
ns
13
Setup time, SCL high before SDA high (for STOP condition)
4
0.6
14
Pulse duration, spike (must be suppressed)
0
50
15
Capacitive load for each bus line
400
400
pF
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
A Fast-mode I2C-bus
device can be used in a Standard-mode I2C-bus
system, but the requirement tsu(SDASCLH)
≥
250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period
of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDASCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode
I2C-Bus Specification) before the SCL line is released.
§A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined
region of the falling edge of SCL.
The maximum th(SDASCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
#Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
10
8
4
3
7
12
5
6
14
2
3
13
Stop
Start
Repeated
Start
Stop
SDA
SCL
1
11
9
Figure 121. I2C Receive Timings
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