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| 型號： | TMX320C6412GNZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Signal Processor |
| 中文描述： | 信號處理器 |
| 文件頁數(shù)： | 69/159頁 |
| 文件大?。?/td> | 1989K |
| 代理商： | TMX320C6412GNZ |
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Terminal Functions
69
April 2003 Revised June 2004
SPRS219D
Table 210. Terminal Functions (Continued)
SIGNAL
DESCRIPTION
IPU
TYPE
NAME
IPD/
GDK/
GNZ
EMIFA (64-BIT) CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY (CONTINUED)
ABE7
T22
O/Z
IPU
ABE6
T23
O/Z
IPU
EMIFA byte-enable control
Decoded from the low-order address bits. The number of address bits or byte
enables
Byte-write enables for most types of memory
Can be directly connected to SDRAM read and write mask signal (SDQM)
ABE5
R25
O/Z
IPU
ABE4
R26
O/Z
IPU
ABE3
M25
O/Z
IPU
ABE2
M26
O/Z
IPU
used depends on the width of external memory.
ABE1
L23
O/Z
IPU
ABE0
L24
O/Z
IPU
APDT
M22
O/Z
IPU
EMIFA peripheral data transfer, allows direct transfer between external peripherals
EMIFA (64-BIT) BUS ARBITRATION
AHOLDA
N22
O
IPU
EMIFA hold-request-acknowledge to the host
AHOLD
W24
I
IPU
EMIFA hold request from the host
ABUSREQ
P22
O
IPU
EMIFA bus request output
EMIFA (64-BIT) ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
AECLKIN
H25
I
IPD
EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6
clock) is selected at reset via the pullup/pulldown resistors on the AEA[20:19] pins.
AECLKIN is the default for the EMIFA input clock.
AECLKOUT2
J23
O/Z
IPD
EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN, CPU/4 clock,
or CPU/6 clock) frequency divided-by-1, -2, or -4.
AECLKOUT1
J26
O/Z
IPD
EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock)
frequency].
AARE/
ASDCAS/
ASADS/ASRE
J25
O/Z
IPU
EMIFA
strobe/programmable synchronous interface-address strobe or read-enable
For programmable synchronous interface, the RENEN field in the CE Space
Secondary
Control Register (CExSEC) selects between ASADS and ASRE:
If RENEN = 0, then the ASADS/ASRE signal functions as the ASADS signal.
If RENEN = 1, then the ASADS/ASRE signal functions as the ASRE signal.
asynchronous
memory
read-enable/SDRAM
column-address
AAOE/
ASDRAS/
ASOE
J24
O/Z
IPU
EMIFA
strobe/programmable synchronous interface output-enable
asynchronous
memory
output-enable/SDRAM
row-address
AAWE/
ASDWE/
ASWE
K26
O/Z
IPU
EMIFA asynchronous memory write-enable/SDRAM write-enable/programmable
synchronous interface write-enable
ASDCKE
L25
O/Z
IPU
EMIFA SDRAM clock-enable (used for self-refresh mode). [EMIFA module only.]
If SDRAM is not in system, ASDCKE can be used as a general-purpose output.
ASOE3
R22
O/Z
IPU
EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO interface)
AARDY
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin.
#A = Analog signal (PLL Filter)
||The EMU0 and EMU1 pins are internally pulled up with 30-k
resistors; therefore, for emulation and normal operation, no external
pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-k
resistor.
L22
I
IPU
Asynchronous memory ready input
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