參數(shù)資料
型號： TMX320C6412GNZ
廠商： Texas Instruments, Inc.
英文描述： Signal Processor
中文描述： 信號處理器
文件頁數(shù)： 68/159頁
文件大?。?/td> 1989K
代理商： TMX320C6412GNZ
Terminal Functions
68
April 2003 Revised June 2004
SPRS219D
Table 210. Terminal Functions (Continued)
SIGNAL
DESCRIPTION
IPU
TYPE
NAME
IPD/
GDK/
GNZ
HOST-PORT INTERFACE (HPI) OR PERIPHERAL COMPONENT INTERCONNECT (PCI) OR EMAC (CONTINUED)
PCBE0
V4
I/O/Z
PCI command/byte enable 0 (
I/O/Z
). When PCI is disabled (PCI_EN = 0), this pin is
tied-off.
GP0[15]/PRST§
G3
I/O/Z
General-purpose input/output (GP0) 15 pin (
I/O/Z
) or PCI reset (
I
). No function at
default.
XSP_CS
T4
O
IPD
PCI serial interface chip select (
O
). When PCI is disabled (PCI_EN = 0), this pin is
tied-off.
XSP_CLK/MDCLK§
R5
I/O/Z
IPD
PCI serial interface clock (
O
) [default] or MDIO serial clock input/output (
I/O/Z
).
XSP_DI
R4
I
IPU
PCI serial interface data in (
I
) [default]. In PCI mode, this pin is connected to the output
data pin of the serial PROM.
XSP_DO/MDIO§
P5
I/O/Z
IPU
PCI serial interface data out (
O
) [default] or MDIO serial data input/output (
I/O/Z
). In PCI
mode, this pin is connected to the input data pin of the serial PROM.
GP0[14]/PCLK§
GP0[13]/PINTA§
GP0[12]/PGNT§
GP0[11]/PREQ§
GP0[10]/PCBE3§
GP0[9]/PIDSEL§
C1
GP0 14 pin (
I/O/Z
) or PCI clock (
I
). No function at default.
GP0 13 pin (
I/O/Z
) or PCI interrupt A (
O/Z
). No function at default.
GP0 12 pin (
I/O/Z
) or PCI bus grant (
I
). No function at default.
GP0 11 pin (
I/O/Z
) or PCI bus request (
O/Z
). No function at default.
GP0 10 pin (
I/O/Z
) or PCI command/byte enable 3 (
I/O/Z
). No function at default.
GP0 9 pin (
I/O/Z
) or PCI initialization device select (
I
). No function at default.
G4
H4
I/O/Z
F1
J2
K3
GP0[3]/PCIEEAI
L5
I/O/Z
IPD
GP0 3 pin (
I/O/Z
) and PCI EEPROM Auto-Initialization (EEAI).
If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must
not
be pulled up.
0
PCI auto-initialization through EEPROM is disabled (default).
1
PCI auto-initialization through EEPROM is enabled.
GP0[8]/PCI66§
AD1
I/O/Z
IPD
This pin can be programmed as a GP0 8 pin (
I/O/Z
) or PCI frequency selection (PCI66).
If the PCI peripheral is enabled (PCI_EN pin = 1), then:
0
PCI operates at 66 MHz (default).
1
PCI operates at 33 MHz.
The -500 device supports PCI at 33 MHz only. For proper -500 device operation when
the PCI peripheral is enabled (PCI_EN = 1), this pin
must
be pulled up with a 1-k
resistor at device reset.
If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must
not
be pulled up.
EMIFA (64-BIT) CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
L26
O/Z
IPU
EMIFA memory space enables
K24
O/Z
IPU
K25
O/Z
IPU
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin.
#A = Analog signal (PLL Filter)
||The EMU0 and EMU1 pins are internally pulled up with 30-k
resistors; therefore, for emulation and normal operation, no external
pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-k
resistor.
ACE3
ACE2
K23
O/Z
IPU
ACE1
Enabled by bits 28 through 31 of the word address
Only one pin is asserted during any external data access
ACE0
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