參數(shù)資料
型號(hào): TMX320C6412GNZ
廠商: Texas Instruments, Inc.
英文描述: Signal Processor
中文描述: 信號(hào)處理器
文件頁數(shù): 112/159頁
文件大?。?/td> 1989K
代理商: TMX320C6412GNZ
Input and Output Clocks
112
April 2003 Revised June 2004
SPRS219D
Table 48. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the
EMIFA Module
(see Figure 410)
NO.
PARAMETER
500
600
UNIT
MIN
MAX
1
tw(EKO2H)
tw(EKO2L)
tt(EKO2)
td(EKIH-EKO2H)
td(EKIH-EKO2L)
The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
N = the EMIF input clock divider; N = 1, 2, or 4.
§This cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
Pulse duration, AECLKOUT2 high
0.5NE 0.7
0.5NE + 0.7
ns
2
Pulse duration, AECLKOUT2 low
0.5NE 0.7
0.5NE + 0.7
ns
3
Transition time, AECLKOUT2
1
ns
4
Delay time, AECLKIN high to AECLKOUT2 high
1
8
ns
5
Delay time, AECLKIN high to AECLKOUT2 low
1
8
ns
4
5
1
2
AECLKIN
AECLKOUT2
3
3
Figure 410. AECLKOUT2 Timing for the EMIFA Module
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