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參數(shù)資料
| 型號(hào)： | SYM53C810A |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器） |
| 文件頁數(shù)： | 97/188頁 |
| 文件大小： | 1120K |
| 代理商： | SYM53C810A |
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Operating Registers
SYM53C810A Data Manual
5-39
Bit 5
SE L (Selected)
T his bit is set when the SYM53C810A is
selected by another SCSI device. T he Enable
Response to Selection bit must have been set in
the SCID register (and the RESPID register
must hold the chip’s ID) for the
SYM53C810A to respond to selection
attempts.
Bit 4
RSL (Reselected)
T his bit is set when the SYM53C810A is rese-
lected by another SCSI device. T he Enable
Response to Reselection bit must have been set
in the SCID register (and the RESPID register
must hold the chip’s ID) for the
SYM53C810A to respond to reselection
attempts.
Bit 3
SGE (SCSI Gross E rror)
T his bit is set when the SYM53C810A
encounters a SCSI Gross Error Condition.
T he following conditions can result in a SCSI
Gross Error Condition:
1. Data Underflow - the SCSI FIFO register
was read when no data was present.
2. Data Overflow - too many bytes were
written to the SCSI FIFO or the
synchronous offset caused the SCSI FIFO
to be overwritten.
3. Offset Underflow - the SYM53C810A is
operating in target mode and a SACK /
pulse is received when the outstanding
offset is zero.
4. Offset Overflow - the other SCSI device
sent a SREQ/ or SACK / pulse with data
which exceeded the maximum
synchronous offset defined by the SX FER
register.
5. A phase change occurred with an
outstanding synchronous offset when the
SYM53C810A was operating as an
initiator.
6. Residual data in the Synchronous data
FIFO - a transfer other than synchronous
data receive was started with data left in the
synchronous data FIFO.
Bit 2
UDC (Unexpected Disconnect)
T his bit is set when the SYM53C810A is oper-
ating in initiator mode and the target device
unexpectedly disconnects from the SCSI bus.
T his bit is only valid when the SYM53C810A
operates in the initiator mode. When the
SYM53C810A operates in low level mode, any
disconnect will cause an interrupt, even a valid
SCSI disconnect. T his bit will also be set if a
selection time-out occurs (it may occur before,
at the same time, or stacked after the ST O
interrupt, since this is not considered an
expected disconnect).
Bit 1
RST (SCSI RST / Received)
T his bit is set when the SYM53C810A detects
an active SRST / signal, whether the reset was
generated external to the chip or caused by the
Assert SRST / bit in the SCNT L1 register. T his
SYM53C810A SCSI reset detection logic is
edge-sensitive, so that multiple interrupts will
not be generated for a single assertion of the
SRST / signal.
Bit 0
PAR (Parity E rror)
T his bit is set when the SYM53C810A detects
a parity error while receiving SCSI data. T he
Enable Parity Checking bit (bit 3 in the
SCNT L0 register) must be set for this bit to
become active. T he SYM53C810A always gen-
erates parity when sending SCSI data.
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