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參數(shù)資料
| 型號(hào)： | SYM53C810A |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器） |
| 文件頁(yè)數(shù)： | 131/188頁(yè) |
| 文件大?。?/td> | 1120K |
| 代理商： | SYM53C810A |
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Instruction Set of the I/O Processor
Memory Move Instructions
SYM53C810A Data Manual
6-23
T he DSPS and DSA registers are additional hold-
ing registers used during the Memory Move; how-
ever, the contents of the DSA register are
preserved.
First Dword
Bits 31-30 Instruction Type - Memory Move
Instruction
Bits 29-25 Reserved
T hese bits are reserved and must be zero. If
any of these bits is set, an illegal instruction
interrupt will occur.
Bit 24
No Flush
Note: this bit has no effect unless the Pre-fetch
Enable bit in the DCNT L register is set.
For information on SCRIPT S instruction
prefetching, see Chapter 2.
When this bit is set, the SYM53C810A per-
forms a Memory Move (MMOV) without
flushing the prefetch unit (NFMMOV). When
this bit is clear, the Memory Move instruction
automatically flushes the prefetch unit. NFM-
MOV should be used if the source and destina-
tion are not within four instructions of the
current MMOV instruction.
Bits 23-0 Transfer Count
T he number of bytes to be transferred is stored
in the lower 24 bits of the first instruction
word.
Second Dword
Bits 31-0, DSPS Register
T hese bits contain the source address of the
Memory Move.
T hird Dword
Bits 31-0, T E MP Register
T hese bits contain the destination address for
the Memory Move.
Read/Write System
Memory from a SCRIPT S Instruction
By using the Memory Move instruction, single or
multiple register values may be transferred to or
from system memory.
Because the SYM53C810A will respond to
addresses as defined in the Base I/O or Base Mem-
ory registers, it could be accessed during a Mem-
ory Move operation if the source or destination
address decodes to within the chip’s register space.
If this occurs, the register indicated by the lower
seven bits of the address is taken to be the data
source or destination. In this way, register values
can be saved to system memory and later restored,
and SCRIPT S can make decisions based on data
values in system memory.
T he SFBR is not writable via the CPU, and there-
fore not by a Memory Move. However, it can be
loaded via SCRIPT S Read/Write operations. To
load the SFBR with a byte stored in system mem-
ory, the byte must first be moved to an intermedi-
ate SYM53C810A register (for example, a
SCRAT CH register), and then to the SFBR.
T he same address alignment restrictions apply to
register access operations as to normal mem-
ory-to-memory transfers.
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