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Operating Registers
5-32
SYM53C810A Data Manual
T his function is useful for register-to-memory
operations using the Memory Move instruc-
tion when the SYM53C810A is I/O mapped.
Bits 4 and 5 of the CT EST 2 register can be
used to determine the configuration status of
the SYM53C810A.
Bit 4
DIOM (Destination I/O-Memory
E nable)
T his bit is defined as an I/O Memory Enable
bit for the destination address of a Memory
Move or Block Move Command. If this bit is
set, then the destination address is in I/O
space; and if reset, then the destination address
is in memory space.
T his function is useful for memory–to–register
operations using the Memory Move instruc-
tion when the SYM53C810A is I/O mapped.
Bits 4 and 5 of the CT EST 2 register can be
used to determine the configuration status of
the SYM53C810A.
Bit 3
E RL (E nable Read Line)
T his bit enables a PCI Read Line command. If
PCI cache mode is enabled by setting bits in
the PCI Cache Line Size register, the chip
issues a Read Line command on all read cycles
if other conditions are met. For more informa-
tion on these conditions, refer to Chapter 3.
E RMP (E nable Read Multiple)
T his bit, when set, will cause Read Multiple
commands to be issued on the PCI bus after
certain conditions have been met. T hese condi-
tions are described in Chapter 3.
Bit 1
BOF (Burst Op Code Fetch E nable)
Setting this bit causes the SYM53C810A to
fetch instructions in burst mode, if the Burst
Disable bit (CT EST 4, bit7) is cleared. Specifi-
cally, the chip will burst in the first two dwords
of all instructions using a single bus ownership.
If the instruction is a memory-to-memory
move type, the third dword will be accessed in
a subsequent bus ownership. If the instruction
is an indirect type, the additional dword will be
accessed in a subsequent bus ownership. If the
instruction is a table indirect block move type,
the chip will access the remaining two dwords
in a subsequent bus ownership, thereby fetch-
ing the four dwords required in two bursts of
two dwords each.
Bit 0
MAN (Manual Start Mode)
Setting this bit prevents the SYM53C810A
from automatically fetching and executing
SCSI SCRIPT S when the DSP register is writ-
ten. When this bit is set, the Start DMA bit in
the DCNT L register must be set to begin
SCRIPT S execution. Clearing this bit causes
the SYM53C810A to automatically begin
fetching and executing SCSI SCRIPT S when
the DSP register is written. T his bit is not nor-
mally used for SCSI SCRIPT S operations.
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