- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385894 > SYM53C810A (LSI Corporation) PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) PDF資料下載
參數(shù)資料
| 型號： | SYM53C810A |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個PCI -的SCSI的I / O接口處理器） |
| 文件頁數(shù)： | 24/188頁 |
| 文件大?。?/td> | 1120K |
| 代理商： | SYM53C810A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁
Functional Description
SDMS: The Total SCSI Solution
2-2
SYM53C810A Data Manual
SDMS: T he Total SCSI
Solution
For users who do not need to develop custom driv-
ers, Symbios Logic provides a total SCSI solution
in PC environments with the SCSI Device Man-
agement System (SDMS). SDMS provides BIOS
and driver support for hard disk, tape, and remov-
able media peripherals for the major PC-based
operating systems.
SDMS includes a SCSI BIOS to manage all SCSI
functions related to the device. It also provides a
series of SCSI device drivers that support most
major operating systems. SDMS supports a multi-
threaded I/O application programming interface
(API) for user-developed SCSI applications.
SDMS supports both the ASPI and CAM SCSI
software specifications.
Prefetching SCRIPT S
Instructions
When enabled (by setting the Prefetch Enable bit
in the DCNT L register), the prefetch logic in the
SYM53C810A fetches 4 or 8 dwords of instruc-
tions. T he prefetch logic automatically determines
the maximum burst size that it can perform, based
on the burst length as determined by the values in
the DMODE register and the PCI Cache Line Size
register (if cache mode is enabled). If the unit can-
not perform bursts of at least four dwords, it will
disable itself.
T he SYM53C810A may flush the contents of the
prefetch unit under certain conditions, listed
below, to ensure that the chip always operates from
the most current version of the software. When one
of these conditions apply, the contents of the
prefetch unit are flushed automatically.
1. On every Memory Move instruction. T he
Memory Move (MMOV) instruction is often
used to place modified code directly into
memory. To make sure that the chip executes
all recent modifications, the prefetch unit
flushes its contents and loads the modified
code every time a MMOV instruction is issued.
To avoid inadvertently flushing the prefetch
unit contents, use the No Flush Memory to
Memory Move (NFMMOV) instruction for all
MMOV operations that do not modify code
within the next 4 to 8 dwords. For more
information on this instruction, refer to
Chapter 6.
2. On every Store instruction. T he Store
instruction may also be used to place modified
code directly into memory. To avoid
inadvertently flushing the prefetch unit
contents, use the No Flush option for all Store
operations that do not modify code within the
next 8 dwords.
3. On every write to the DSP register.
4. On all Transfer Control instructions when the
transfer conditions are met. T his is necessary
because the next instruction to be executed is
not the sequential next instruction in the
prefetch unit.
5. When the Pre-Fetch Flush bit (DCNT L bit 5)
is set. T he unit flushes whenever this bit is set.
T he bit is self-clearing.
Op Code Fetch
Burst Capability
Setting the Burst Op Code Fetch Enable bit in the
DMODE register (38h) causes the SYM53C810A
to burst in the first two dwords of all instruction
fetches. If the instruction is a memory-to-memory
move, the third dword will be accessed in a sepa-
rate ownership. If the instruction is an indirect
type, the additional dword will be accessed in a
subsequent bus ownership. If the instruction is a
table indirect Block Move, the SYM53C810A will
use two accesses to obtain the four dwords
required, in two bursts of two dwords each.
Note: this feature can only be used if SCRIPT S
pre-fetching is disabled.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SYM53C825A | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| SYM53C825AE | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| SYM53C860 | Single-Chip High-Performance PCI-Ultra SCSI (Fast-20) I/O Processor(單片、高性能PCI-超級SCSI (Fast-20) I/O 處理器) |
| SYM53C875 | PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O處理器) |
| SYM53C875E | PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O 處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SYM53C876E(PBGA) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SCSI Bus Interface/Controller |
| SYM53C876E(PQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SCSI Bus Interface/Controller |
| SYM53C885 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| SYM53C896 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
| SYM-63LH+ | 制造商:MINI 制造商全稱:Mini-Circuits 功能描述:Frequency Mixer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。