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參數(shù)資料
| 型號： | SYM53C810A |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個PCI -的SCSI的I / O接口處理器） |
| 文件頁數(shù)： | 41/188頁 |
| 文件大?。?/td> | 1120K |
| 代理商： | SYM53C810A |
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PCI Functional Description
PCI Cache Mode
SYM53C810A Data Manual
3-3
Memory Write
and Invalidate Command
T he Memory Write and Invalidate command is
identical to the Memory Write command, except
that it additionally guarantees a minimum transfer
of one complete cache line; i.e., the master intends
to write all bytes within the addressed cache line in
a single PCI transaction unless interrupted by the
target. T his command requires implementation of
the PCI Cache Line Size register at address 0Ch in
PCI configuration space. T he SYM53C810A
enables Memory Write and Invalidate cycles when
bit 0 in the CT EST 3 register (WRIE) and bit 4 in
the PCI Command register are set. T his will cause
Memory Write and Invalidate commands to be
issued when the following conditions are met:
1. T he CLSE bit, WRIE bit, and PCI Config
Command register, bit 4 must be set.
2. T he cache line size register must contain a
legal burst size (2, 4, 8 or 16) value AND that
value must be less than or equal to the
DMODE burst size.
3. T he chip must have enough bytes in the DMA
FIFO to complete at least one full cache line
burst.
4. T he chip must be aligned to a cache line
boundary.
When these conditions have been met, the
SYM53C810A will issue a Write and Invalidate
command instead of a Memory Write command
during all PCI write cycles.
Multiple Cache Transfers
When multiple cache lines of data have been
read in during a MMOV instruction (See the
description for the Read Multiple command),
the SYM53C810A will issue a Write and Inval-
idate command using the burst size necessary
to transfer all the data in one transfer. For
example, if the cache line size is 4, and the chip
read in 16 dwords of data using a Read Multi-
ple command, the chip will switch the burst
size to 16, and issue a Write and Invalidate to
transfer all 16 dwords in one bus ownership.
Latency
In accordance with the PCI specification, the
chip's latency timer will be ignored when issuing a
Write and Invalidate command such that when a
latency time-out has occurred, the SYM53C810A
will continue to transfer up until a cache line
boundary. At that point, the chip will relinquish
the bus, and finish the transfer at a later time using
another bus ownership. If the chip is transferring
multiple cache lines it will continue to transfer
until the next cache boundary is reached.
PCI Target Retries
During a Write and Invalidate transfer, if the target
device issues a retry (ST OP with no T RDY, indi-
cating that no data was transferred), the
SYM53C810A will relinquish the bus and imme-
diately try to finish the transfer on another bus
ownership. T he chip will issue another Write and
Invalidate command on the next ownership, in
accordance with the PCI specification.
PCI Target Disconnect
During a Write and Invalidate transfer, if the target
device issues a disconnect the SYM53C810A will
relinquish the bus and immediately try to finish the
transfer on another bus ownership. T he chip will
not issue another Write and Invalidate command
on the next ownership.
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