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參數(shù)資料
| 型號： | SYM53C810A |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個PCI -的SCSI的I / O接口處理器） |
| 文件頁數(shù)： | 23/188頁 |
| 文件大?。?/td> | 1120K |
| 代理商： | SYM53C810A |
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Functional Description
SCSI Core
SYM53C810A Data Manual
2-1
Chapter 2
Functional Description
T he SYM53C810A contains three functional
blocks: the SCSI Core, the DMA Core, and the
SCRIPT S Processor. T he SYM53C810A is fully
supported by the SCSI Device Management Sys-
tem (SDMS), a complete software package that
supports the Symbios Logic product line of SCSI
processors and controllers.
SCSI Core
T he SCSI core supports , synchronous transfer
rates up to 10 MB/s, and asynchronous transfer
rates up to 7 MB/s on an 8-bit SCSI bus. T he
SCSI core can be programmed with SCSI
SCRIPT S, making it easy to fine tune the system
for specific mass storage devices or advanced SCSI
requirements.
T he SCSI core offers low-level register access or a
high-level control interface. Like first generation
SCSI devices, the SYM53C810A SCSI core can
be accessed as a register-oriented device. T he abil-
ity to sample and/or assert any signal on the SCSI
bus can be used in error recovery and diagnostic
procedures. In support of loopback diagnostics,
the SCSI core can perform a self-selection and
operate as both an initiator and a target.
T he SCSI core is controlled by the integrated
SCRIPT S processor through a high-level logical
interface. Commands controlling the SCSI core
are fetched out of the main host memory or local
memory. T hese commands instruct the SCSI core
to Select, Reselect, Disconnect, Wait for a Discon-
nect, Transfer Information, Change Bus Phases
and, in general, implement all aspects of the SCSI
protocol. T he SCRIPT S processor is a special
high-speed processor optimized for SCSI protocol.
DMA Core
T he DMA core is a bus master DMA device that
attaches directly to the industry standard PCI Bus.
T he DMA core is tightly coupled to the SCSI core
through the SCRIPT S processor, which supports
uninterrupted scatter/gather memory operations.
T he SYM53C810A supports 32-bit memory and
automatically supports misaligned DMA transfers.
An 80-byte FIFO allows two, four, eight, or six-
teen dword bursts across the PCI bus interface to
run efficiently without throttling the bus during
PCI bus latency.
SCRIPT S Processor
T he SCSI SCRIPT S processor allows both DMA
and SCSI commands to be fetched from host
memory. Algorithms written in SCSI SCRIPT S
control the actions of the SCSI and DMA cores
and are executed from 32-bit system RAM. T he
SCRIPT S processor executes complex SCSI bus
sequences independently of the host
CPU.
T he SCRIPT S processor can begin a SCSI I/O
operation in approximately 500 ns. T his compares
with 2-8 ms required for traditional intelligent host
adapters. Algorithms may be designed to tune
SCSI bus performance, to adjust to new bus device
types (such as scanners, communication gateways,
etc.), or to incorporate changes in the SCSI-2 or
SCSI-3 logical bus definitions without sacrificing
I/O performance. SCSI SCRIPT S are hardware
independent, so they can be used interchangeably
on any host or CPU system bus.
A complete set of development tools is available for
writing custom drivers with SCSI SCRIPT S. For
more information on SCSI SCRIPT S instructions
supported by the SYM53C810A, see Chapter 6.
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