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參數(shù)資料
| 型號： | SYM53C810A |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個PCI -的SCSI的I / O接口處理器） |
| 文件頁數(shù)： | 42/188頁 |
| 文件大?。?/td> | 1120K |
| 代理商： | SYM53C810A |
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PCI Functional Description
PCI Cache Mode
3-4
SYM53C810A Data Manual
Memory Read
Line Command
T his command is identical to the Memory Read
command, except that it additionally indicates that
the master intends to fetch a complete cache line.
T his command is intended to be used with bulk
sequential data transfers where the memory system
and the requesting master might gain some perfor-
mance advantage by reading up to a cache line
boundary rather than a single memory cycle.T he
Read Line Mode function that exists in the previ-
ous SYM53C8X X chips has been modified in the
SYM53C810A to reflect the PCI cache line size
register specifications. T he functionality of the
Enable Read Line bit (bit 3 in DMODE) has been
modified to more resemble the Write and Invali-
date mode in terms of conditions that must be met
before a Read Line command will be issued. How-
ever, the Read Line option will operate exactly like
the previous SYM53C8X X chips when cache
mode has been disabled by a CLSE bit reset or
when certain conditions exist in the chip
(explained below).
T he Read Line mode is enabled by setting bit 3 in
the DMODE register. If cache mode is disabled,
Read Line commands will be issued on every read
data transfer, except op code fetches, as in previ-
ous SYM53C8X X chips.
If cache mode has been enabled, a Read Line com-
mand will be issued on all read cycles, except op
code fetches, when the following conditions have
been met:
1. T he CLSE and Enable Read Line bits must be
set.
2. T he Cache Line Size register must contain a
legal burst size value (2, 4, 8 or 16) AND that
value must be less than or equal to the
DMODE burst size.
3. T he number of bytes to be transferred at the
time a cache boundary has been reached must
be equal to or greater than a full cache line
size.
4. T he chip must be aligned to a cache line
boundary.
When these conditions have been met, the chip
will issue a Read Line command instead of a
Memory Read during all PCI read cycles. Other-
wise, it will issue a normal Memory Read com-
mand.
Memory Read
Multiple Command
T his command is identical to the Memory read
command except that it additionally indicates that
the master may intend to fetch more than one
cache line before disconnecting. T he
SYM53C810A supports PCI Read Multiple func-
tionality and will issue Read Multiple commands
on the PCI bus when the Read Multiple Mode is
enabled. T his mode is enabled by setting bit 2 of
the DMODE register (ERMP). T he command will
be issued when certain conditions have been met.
If cache mode has been enabled, a Read Multiple
command will be issued on all read cycles, except
op code fetches, when the following conditions
have been met:
1. T he CLSE and ERMP bits must be set.
2. T he Cache Line Size register must contain a
legal burst size value (2, 4, 8 or 16) AND that
value must be less than or equal to the
DMODE burst size.
3. T he number of bytes to be transferred at the
time a cache boundary has been reached must
be equal to or greater than the DMODE burst
size.
4. T he chip must be aligned to a cache line
boundary.
When these conditions have been met, the chip
will issue a Read Multiple command instead of a
Memory Read during all PCI read cycles.
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