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參數(shù)資料
| 型號(hào)： | SYM53C810A |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器） |
| 文件頁數(shù)： | 119/188頁 |
| 文件大?。?/td> | 1120K |
| 代理商： | SYM53C810A |
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Instruction Set of the I/O Processor
I/O Instructions
SYM53C810A Data Manual
6-11
Clear Instruction
When the SACK / or SAT N/ bits are set, the corre-
sponding bits are cleared in the SOCL register.
SACK / or SAT N/ should not be set except for test-
ing purposes. When the target bit is set, the corre-
sponding bit in the SCNT L0 register is cleared.
When the carry bit is set, the corresponding bit in
the ALU is cleared.
Note: none of the signals are reset on the SCSI
bus in target mode.
Initiator Mode
Select Instruction
1. T he SYM53C810A arbitrates for the SCSI bus
by asserting the SCSI ID stored in the SCID
register. If the SYM53C810A loses arbitration,
it tries again during the next available
arbitration cycle without reporting any lost
arbitration status.
2. If the SYM53C810A wins arbitration, it
attempts to select the SCSI device whose ID is
defined in the destination ID field of the
instruction. Once the SYM53C810A has won
arbitration, it fetches the next instruction from
the address pointed to by the DSP register.
T herefore, the SCRIPT S program can move to
the next instruction before the selection has
completed. It will continue executing
SCRIPT S until a SCRIPT S instruction that
requires a response from the target is
encountered.
3. If the SYM53C810A is selected or reselected
before winning arbitration, it fetches the next
instruction from the address pointed to by the
OPC2
OPC1
OPC0
Instruction Defined
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Select
Wait Disconnect
Wait Reselect
Set
Clear
32-bit jump address field stored in the DNAD
register. T he SYM53C810A should manually
be set to initiator mode if it is reselected, or to
target mode if it is selected.
4. If the Select with SAT N/ field is set, the
SAT N/ signal is asserted during the selection
phase.
Wait Disconnect Instruction
1. T he SYM53C810A waits for the target to
perform a “l(fā)egal” disconnect from the SCSI
bus. A “l(fā)egal” disconnect occurs when SBSY/
and SSEL/ are inactive for a minimum of one
Bus Free delay (400 ns), after the
SYM53C810A has received a Disconnect
Message or a Command Complete Message.
Wait Reselect Instruction
1. If the SYM53C810A is selected before being
reselected, it fetches the next instruction from
the address pointed to by the 32-bit jump
address field stored in the DNAD register. T he
SYM53C810A should be manually set to
target mode when selected.
2. If the SYM53C810A is reselected, it fetches
the next instruction from the address pointed
to by the DSP register.
3. If the CPU sets the SIGP bit in the ISTAT
register, the SYM53C810A will abort the Wait
Reselect instruction and fetch the next
instruction from the address pointed to by the
32-bit jump address field stored in the DNAD
register.
Set Instruction
When the SACK / or SAT N/ bits are set, the corre-
sponding bits in the SOCL register are set. When
the Target bit is set, the corresponding bit in the
SCNT L0 register is also set. When the Carry bit is
set, the corresponding bit in the ALU is set.
Clear Instruction
When the SACK /or SAT N/ bits are set, the corre-
sponding bits are cleared in the SOCL register.
When the Target bit is set, the corresponding bit in
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