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參數(shù)資料
| 型號： | SYM53C810A |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個PCI -的SCSI的I / O接口處理器） |
| 文件頁數(shù)： | 109/188頁 |
| 文件大?。?/td> | 1120K |
| 代理商： | SYM53C810A |
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Instruction Set of the I/O Processor
SCSI SCRIPTS
SYM53C810A Data Manual
6-1
Chapter 6
Instruction Set of the I/O Processor
After power up and initialization of the
SYM53C810A, the chip can operate in the low
level register interface mode, or using SCSI
SCRIPT S.
With the low level register interface, the user has
access to the DMA control logic and the SCSI bus
control logic. An external processor has access to
the SCSI bus signals and the low level DMA sig-
nals, which allows creation of complicated board
level test algorithms. T he low level interface is use-
ful for backward compatibility with SCSI devices
that require certain unique timings or bus
allowed at the low level is loopback testing. In
loopback mode, the SCSI core can be directed to
talk to the DMA core to test internal data paths all
the way out to the chip’s pins.
SCSI SCRIPT S
To operate in the SCSI SCRIPT S mode, the
SYM53C810A requires only a SCRIPT S start
address. T he start address must be at a dword
(four byte) boundary. T his aligns the following
SCRIPT S at a dword boundary, since all
SCRIPT S are 8 or 12 bytes long. All instructions
are fetched from external memory. T he
SYM53C810A fetches and executes its own
instructions by becoming a bus master on the host
bus and fetching two or three 32-bit words into its
registers. Instructions are fetched until an inter-
rupt instruction is encountered, or until an unex-
pected event (such as a hardware error) causes an
interrupt to the external processor.
Once an interrupt is generated, the SYM53C810A
halts all operations until the interrupt is serviced.
T hen, the start address of the next SCRIPT S
instruction may be written to the DMA SCRIPT S
Pointer register to restart the automatic fetching
and execution of instructions.
T he SCSI SCRIPT S mode of execution allows the
SYM53C810A to make decisions based on the sta-
tus of the SCSI bus, so that the microprocessor
does not have to service all of the interrupts inher-
ent in I/O operations.
Given the rich set of SCSI-oriented features
included in the instruction set, and the ability to
re-enter the SCSI algorithm at any point, this high
level interface is all that is required for both normal
and exception conditions. T here is no need to
switch to low level mode for error recovery.
Five types of SCRIPT S instructions are imple-
mented in the SYM53C810A:
I
Block Move—used to move data between the
SCSI bus and memory
I
I/O or Read/Write—causes the SYM53C810A
to trigger common SCSI hardware sequences,
or to move registers
I
Transfer Control— allows SCRIPT S
instructions to make decisions based on real
time SCSI bus conditions
I
Memory Move— causes the SYM53C810A to
execute block moves between different parts of
main memory
I
Load and Store—provides a more efficient way
to move data to/from memory from/to an
internal register in the chip without using the
Memory Move instruction.
Each instruction consists of two or three 32-bit
words. T he first 32-bit word is always loaded into
the DCMD and DBC registers, the second into
the DSPS register. T he third word, used only by
Memory Move instructions, is loaded into the
T EMP shadow register. In an indirect I/O or Move
instruction, the first two 32-bit op code fetches will
be followed by one or two more 32-bit fetch cycles.
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