參數(shù)資料
型號(hào)： SYM53C810A
廠商： LSI Corporation
英文描述： PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器)
中文描述： 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器）
文件頁(yè)數(shù)： 65/188頁(yè)
文件大小： 1120K
代理商： SYM53C810A
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Operating Registers
SYM53C810A Data Manual
5-7
Register 01 (81)
SCSI Control One (SCNT L1)
Read/Write
Bit 7
E X C (E xtra clock cycle of data
setup)
When this bit is set, an extra clock period of
data setup is added to each SCSI data send
transfer. T he extra data setup time can provide
additional system design margin, though it will
affect the SCSI transfer rates. Clearing this bit
disables the extra clock cycle of data setup
time. Setting this bit only affects SCSI send
operations.
Bit 6
ADB (Assert SCSI data bus)
When this bit is set, the SYM53C810A drives
the contents of the SCSI Output Data Latch
Register (SODL) onto the SCSI data bus.
When the SYM53C810A is an initiator, the
SCSI I/O signal must be inactive to assert the
SODL contents onto the SCSI bus. When the
SYM53C810A is a target, the SCSI I/O signal
must be active for the SODL contents to be
asserted onto the SCSI bus. T he contents of
the SODL register can be asserted at any time,
even before the SYM53C810A is connected to
the SCSI bus. T his bit should be cleared when
executing SCSI SCRIPT S. It is normally used
only for diagnostics testing or operation in low
level mode.
Bit 5
DHP (Disable Halt on Parity E rror
or AT N) (Target Only)
T he DHP bit is only defined for target role.
When this bit is cleared, the SYM53C810A
halts the SCSI data transfer when a parity error
is detected or when the SAT N/ signal is
asserted. If SAT N/ or a parity error is received
in the middle of a data transfer, the
SYM53C810A may transfer up to three addi-
tional bytes before halting to synchronize
between internal core cells. During synchro-
nous operation, the SYM53C810A transfers
data until there are no outstanding synchro-
nous offsets. If the SYM53C810A is receiving
data, any data residing in the DMA FIFO is
sent to memory before halting.
When this bit is set, the SYM53C810A does
not halt the SCSI transfer when SAT N/ or a
parity error is received.
Bit 4
CON (Connected)
T his bit is automatically set any time the
SYM53C810A is connected to the SCSI bus
as an initiator or as a target. It is set after the
SYM53C810A successfully completes arbitra-
tion or when it has responded to a bus initiated
selection or reselection. T his bit is also set after
the chip wins simple arbitration when operat-
ing in low level mode. When this bit is clear,
the SYM53C810A is not connected to the
SCSI bus.
T he CPU can force a connected or discon-
nected condition by setting or clearing this bit.
T his feature would be used primarily during
loopback mode.
Bit 3
RST (Assert SCSI RST / signal)
Setting this bit asserts the SRST / signal. T he
SRST / output remains asserted until this bit is
cleared. T he 25
μ
s minimum assertion time
defined in the SCSI specification must be
timed out by the controlling microprocessor or
a SCRIPT S loop.
Bit 2
AE SP (Assert even SCSI parity
(force bad parity))
When this bit is set, the SYM53C810A asserts
even parity. It forces a SCSI parity error on
each byte sent to the SCSI bus from the
SYM53C810A. If parity checking is enabled,
then the SYM53C810A checks data received
for odd parity. T his bit is used for diagnostic
testing and should be clear for normal opera-
tion. It can be used to generate parity errors to
test error handling functions.
EXC
7
ADB
6
DHP
5
CON
4
RST
3
AESP
2
IARB
1
SST
0
Default>>>
0
0
0
0
0
0
0
0
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