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參數(shù)資料
| 型號： | SYM53C810A |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個PCI -的SCSI的I / O接口處理器） |
| 文件頁數(shù)： | 94/188頁 |
| 文件大?。?/td> | 1120K |
| 代理商： | SYM53C810A |
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Operating Registers
5-36
SYM53C810A Data Manual
Register 40 (C0)
SCSI Interrupt Enable Zero (SIEN0)
Read/Write
T his register contains the interrupt mask bits that
correspond to the interrupting conditions described
in the SIST 0 register. An interrupt is masked by
clearing the appropriate mask bit. For more infor-
mation on interrupts, see Chapter 2.
Bit 7
M/A (SCSI Phase Mismatch -
Initiator Mode; SCSI AT N
Condition - Target Mode)
In initiator mode, this bit controls whether an
interrupt occurs when the SCSI phase asserted
by the target and sampled during SREQ/ does
not match the expected phase in the SOCL
register. T his expected phase is automatically
written by the SCSI SCRIPT S program. In
target mode, this bit is set when the initiator
has asserted SAT N/. See the Disable Halt on
Parity Error or SAT N/ Condition bit in the
SCNT L1 register for more information on
when this status is actually raised.
Bit 6
CMP (Function Complete)
T his bit controls whether an interrupt occurs
when full arbitration and selection sequence
has completed.
Bit 5
SE L (Selected)
T his bit controls whether an interrupt occurs
when the SYM53C810A has been selected by
a SCSI target device. T he Enable Response to
Selection bit in the SCID register must be set
for this to occur.
Bit 4
RSL (Reselected)
T his bit controls whether an interrupt occurs
when the SYM53C810A has been reselected
by a SCSI initiator device. T he Enable
Response to Reselection bit in the SCID regis-
ter must be set for this to occur.
Bit 3
SGE (SCSI Gross E rror)
T his bit controls whether an interrupt occurs
when the SYM53C810A detects a SCSI Gross
Error. T he following conditions are considered
SCSI Gross Errors:
1. Data underflow - the SCSI FIFO was read
when no data was present.
2. Data overflow - the SCSI FIFO was
written to while full.
3. Offset underflow - in target mode, a
SACK / pulse was received before the
corresponding SREQ/ was sent.
4. Offset overflow - in initiator mode, an
SREQ/ pulse was received which caused
the maximum offset (Defined by the
MO3-0 bits in the SX FER register) to be
exceeded.
5. In initiator mode, a phase change occurred
with an outstanding SREQ/SACK offset.
6. Residual data in SCSI FIFO - a transfer
other than synchronous data receive was
started with data left in the SCSI
synchronous receive FIFO.
Bit 2
UDC (Unexpected Disconnect)
T his bit controls whether an interrupt occurs
in the case of an unexpected disconnect. T his
condition only occurs in initiator mode. It hap-
pens when the target to which the
SYM53C810A is connected disconnects from
the SCSI bus unexpectedly. See the SCSI Dis-
connect Unexpected bit in the SCNT L2 regis-
ter for more information on expected versus
unexpected disconnects. Any disconnect in low
level mode causes this condition.
M/A
7
CMP
6
SEL
5
RSL
4
SGE
3
UDC
2
RST
1
PAR
0
Default>>>
0
0
0
0
0
0
0
0
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