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參數(shù)資料
| 型號(hào)： | SYM53C810A |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器） |
| 文件頁(yè)數(shù)： | 114/188頁(yè) |
| 文件大?。?/td> | 1120K |
| 代理商： | SYM53C810A |
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Instruction Set of the I/O Processor
Block Move Instructions
6-6
SYM53C810A Data Manual
Prior to the start of an I/O, the Data Structure
Base Address register (DSA) should be loaded
with the base address of the I/O data structure.
T he address may be any address on a long
word boundary.
After a Table Indirect op code is fetched, the
DSA is added to the 24-bit signed offset value
from the op code to generate the address of the
required data; both positive and negative off-
sets are allowed. A subsequent fetch from that
address brings the data values into the chip.
For a MOVE instruction, the 24-bit byte count
is fetched from system memory. T hen the 32-
bit physical address is brought into the
SYM53C810A. Execution of the move begins
at this point.
SCRIPT S can directly execute operating sys-
tem I/O data structures, saving time at the
beginning of an I/O operation. T he I/O data
structure can begin on any dword boundary
and may cross system segment boundaries.
T here are two restrictions on the placement of
pointer data in system memory: the eight bytes
of data in the MOVE instruction must be con-
tiguous, as shown below; and indirect data
fetches are not available during execution of a
Memory-to-Memory DMA operation.
Bit 27
Op Code
T his 1-bit field defines the instruction to be
executed as a block move (MOVE).
00
Byte Count
Physical Data Address
Target Mode
1. T he SYM53C810A verifies that it is connected
to the SCSI bus as a target before executing
this instruction.
2. T he SYM53C810A asserts the SCSI phase
signals (SMSG/, SC_D/, and SI_O/) as defined
by the Phase Field bits in the instruction.
3. If the instruction is for the command phase,
the SYM53C810A receives the first command
byte and decodes its SCSI Group Code.
a) If the SCSI Group Code is either Group 0,
Group 1, Group 2, or Group 5, then the
SYM53C810A overwrites the DBC
register with the length of the Command
Descriptor Block: 6, 10, or 12 bytes.
b) If any other Group Code is received, the
DBC register is not modified and the
SYM53C810A will request the number of
bytes specified in the DBC register. If the
DBC register contains 000000h, an illegal
instruction interrupt is generated.
4. T he SYM53C810A transfers the number of
bytes specified in the DBC register starting at
the address specified in the DNAD register.
5. If the SAT N/ signal is asserted by the initiator
or a parity error occurred during the transfer,
the transfer can optionally be halted and an
interrupt generated. T he Disable Halt on
Parity Error or AT N bit in the SCNT L1
register controls whether the SYM53C810A
will halt on these conditions immediately, or
wait until completion of the current Move.
OPC
Instruction Defined
0
1
MOVE
Reserved
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