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參數(shù)資料
| 型號： | SYM53C810A |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個PCI -的SCSI的I / O接口處理器） |
| 文件頁數(shù)： | 35/188頁 |
| 文件大小： | 1120K |
| 代理商： | SYM53C810A |
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Functional Description
Interrupt Handling
SYM53C810A Data Manual
2-13
Interrupt Handling
T he SCRIPT S processor in the SYM53C810A
performs most functions independently of the host
microprocessor. However, certain interrupt situa-
tions must be handled by the external micropro-
cessor. T his section explains all aspects of
interrupts as they apply to the SYM53C810A.
Polling and
Hardware Interrupts
T he external microprocessor is informed of an
interrupt condition by polling or hardware inter-
rupts. Polling means that the microprocessor must
continually loop and read a register until it detects
a bit set that indicates an interrupt. T his method is
the fastest, but it wastes CPU time that could be
used for other system tasks. T he preferred method
of detecting interrupts in most systems is hardware
interrupts. In this case, the SYM53C810A will
assert the Interrupt Request (IRQ/) line that will
interrupt the microprocessor, causing the micro-
processor to execute an interrupt service routine. A
hybrid approach would use hardware interrupts for
long waits, and use polling for short waits.
Registers
T he registers in the SYM53C810A that are used
for detecting or defining interrupts are the ISTAT,
SIST 0, SIST 1, DSTAT, SIEN0, SIEN1,
DCNT L, and DIEN.
ISTAT
T he ISTAT is the only register that can be
accessed as a slave during SCRIPT S operation,
therefore it is the register that is polled when
polled interrupts are used. It is also the first regis-
ter that should be read when the IRQ/ pin has been
asserted in association with a hardware interrupt.
T he INT F (Interrupt on the Fly) bit should be the
first interrupt serviced. It must be written to one to
be cleared. T his interrupt must be cleared before
servicing any other interrupts. If the SIP bit in the
ISTAT register is set, then a SCSI-type interrupt
has occurred and the SIST 0 and SIST 1 registers
should be read. If the DIP bit in the ISTAT regis-
ter is set, then a DMA-type interrupt has occurred
and the DSTAT register should be read. SCSI-
type and DMA-type interrupts may occur simulta-
neously, so in some cases both SIP and DIP may
be set.
SIST 0 and SIST 1
T he SIST 0 and SIST 1 registers contain the SCSI-
type interrupt bits. Reading these registers will
determine which condition or conditions caused
the SCSI-type interrupt, and will clear that SCSI
interrupt condition. If the SYM53C810A is receiv-
ing data from the SCSI bus and a fatal interrupt
condition occurs, the SYM53C810A will attempt
to send the contents of the DMA FIFO to memory
before generating the interrupt. If the
SYM53C810A is sending data to the SCSI bus
and a fatal SCSI interrupt condition occurs, data
could be left in the DMA FIFO. Because of this
the DMA FIFO Empty (DFE) bit in DSTAT
should be checked. If this bit is clear, set the CLF
(Clear DMA FIFO) and CSF (Clear SCSI FIFO)
bits before continuing. T he CLF bit is bit 2 in
CT EST 3. T he CSF bit is bit 1 in ST EST 3.
DSTAT
T he DSTAT register contains the DMA-type
interrupt bits. Reading this register will determine
which condition or conditions caused the DMA-
type interrupt, and will clear that DMA interrupt
condition. T he DFE bit, bit 7 in DSTAT, is purely
a status bit; it will not generate an interrupt under
any circumstances and will not be cleared when
read. DMA interrupts will flush neither the DMA
nor SCSI FIFOs before generating the interrupt,
so the DFE bit in the DSTAT register should be
checked after any DMA interrupt. If the DFE bit
is clear, then the FIFOs must be cleared by setting
the CLF (Clear DMA FIFO) and CSF (Clear
SCSI FIFO) bits, or flushed by setting the FLF
(Flush DMA FIFO) bit.
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