參數(shù)資料
型號(hào)： SYM53C810A
廠商： LSI Corporation
英文描述： PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器)
中文描述： 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器）
文件頁(yè)數(shù)： 115/188頁(yè)
文件大?。?/td> 1120K
代理商： SYM53C810A
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Instruction Set of the I/O Processor
Block Move Instructions
SYM53C810A Data Manual
6-7
Initiator Mode
1. T he SYM53C810A verifies that it is connected
to the SCSI bus as an initiator before executing
this instruction.
2. T he SYM53C810A waits for an unserviced
phase to occur. An unserviced phase is defined
as any phase (with SREQ/ asserted) for which
the SYM53C810A has not yet transferred data
by responding with a SACK /.
3. T he SYM53C810A compares the SCSI phase
bits in the DCMD register with the latched
SCSI phase lines stored in the SSTAT 1
register. T hese phase lines are latched when
SREQ/ is asserted.
4. If the SCSI phase bits match the value stored
in the SSTAT 1 register, the SYM53C810A
will transfer the number of bytes specified in
the DBC register starting at the address
pointed to by the DNAD register.
5. If the SCSI phase bits do not match the value
stored in the SSTAT 1 register, the
SYM53C810A generates a phase mismatch
interrupt and the instruction is not executed.
6. During a Message Out phase, after the
SYM53C810A has performed a Select with
Attention (or SAT N/ has been manually
asserted with a Set AT N instruction), the
SYM53C810A will deassert SAT N/ during the
final SREQ/SACK handshake of the first move
of Message Out bytes after SAT N/ was set.
7. When the SYM53C810A is performing a block
move for Message In phase, it will not deassert
the SACK / signal for the last SREQ/SACK
handshake. T he SACK signal must be cleared
using the Clear SACK I/O instruction.
OPC
Instruction Defined
0
1
Reserved
MOVE
Bits 26-24 SCSI Phase
T his 3-bit field defines the desired SCSI infor-
mation transfer phase. When the
SYM53C810A operates in initiator mode,
these bits are compared with the latched SCSI
phase bits in the SSTAT 1 register. When the
SYM53C810A operates in target mode, the
SYM53C810A asserts the phase defined in this
field. T he following table describes the possible
combinations and the corresponding SCSI
phase.
Bits 23-0 Transfer Counter
T his 24-bit field specifies the number of data
bytes to be moved between the SYM53C810A
and system memory. T he field is stored in the
DBC register. When the SYM53C810A trans-
fers data to/from memory, the DBC register is
decremented by the number of bytes trans-
ferred. In addition, the DNAD register is
incremented by the number of bytes trans-
ferred. T his process is repeated until the DBC
register has been decremented to zero. At that
time, the SYM53C810A fetches the next
instruction.
If bit 28 is set, indicating table indirect
addressing, this field is not used. T he byte
count is instead fetched from a table pointed to
by the DSA register.
MSG
C/D
I/O
SCSI Phase
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Data out
Data in
Command
Status
Reserved out
Reserved in
Message out
Message in
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