
Operating Registers
5-14
SYM53C810A Data Manual
Register 07 (87)
General Purpose (GPREG)
Read/Write
Bits 7-2 Reserved
Bits 1-0 GPIO1-GPIO0 (General Purpose)
T hese bits can be programmed through the
GPCNT L Register to become inputs, outputs,
or, special functions. T hese signals can also be
programmed as live inputs and sensed through
a SCRIPT S Register to Register Move Instruc-
tion. GPIO(1-0) default as inputs. When con-
figured as inputs, an internal pull-up is
enabled.
T he Symbios Logic SDMS software uses the
GPIO 0 pin to toggle SCSI device LEDs, turn-
ing on the LED whenever the SYM53C810A
is connected to the SCSI bus. SDMS drives
this pin low to turn on the LED, or drives it
high to turn off the LED.
T he GPIO 1-0 pins are used in SDMS to
access serial NVRAM. When used for access-
ing serial NVRAM, GPIO 1 is used as a clock
with the GPIO 0 pin serving as data.
Register 08 (88)
SCSI First Byte Received (SFBR)
Read/Write
T his register contains the first byte received in any
asynchronous information transfer phase. For ex-
ample, when the SYM53C810A is operating in ini-
tiator role, this register contains the first byte
received in Message In, Status Phase, Reserved In
and Data In.
When a Block Move instruction is executed for a
particular phase, the first byte received is stored in
this register—even if the present phase is the same
as the last phase. T he first byte-received value for a
particular input phase is not valid until after a
MOVE instruction is executed.
T his register is also the accumulator for register
read-modify-writes with the SFBR as the destina-
tion. T his allows bit testing after an operation.
T he SFBR can not be written to via the CPU, and
therefore not by a Memory Move. Additionally, the
Load instruction cannot be used to write to this reg-
ister. However, the SFBR can be loaded via
SCRIPT S Read/Write operations. T o load the
SFBR with a byte stored in system memory, the
byte must first be moved to an intermediate
SYM53C810A register (such as the SCRAT CH
register), and then to the SFBR.
T his register will also contain the state of the lower
eight bits of the SCSI data bus during the selection
phase if the COM bit in the DCNT L register is
clear.
RES
7
RES
6
RES
5
RES
4
RES
3
RES
2
GPIO1
1
GPIO0
0
Default>>>
X
X
X
X
X
X
0
0
1B7
7
1B6
6
1B5
5
1B4
4
1B3
3
1B2
2
1B1
1
1B0
0
Default>>>
0
0
0
0
0
0
0
0