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參數(shù)資料
| 型號(hào)： | SYM53C810A |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器） |
| 文件頁(yè)數(shù)： | 84/188頁(yè) |
| 文件大?。?/td> | 1120K |
| 代理商： | SYM53C810A |
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Operating Registers
5-26
SYM53C810A Data Manual
Register 20 (A0)
DMA FIFO (DFIFO)
Read/Write
Bit 7
Reserved
Bits 6-0 BO6-BO0 (Byte offset counter)
T hese bits indicate the amount of data trans-
ferred between the SCSI core and the DMA
core. It may be used to determine the number
of bytes in the DMA FIFO when an interrupt
occurs. T hese bits are unstable while data is
being transferred between the two cores; once
the chip has stopped transferring data, these
bits are stable.
Since the DFIFO register counts the number
of bytes transferred between the DMA core
and the SCSI core, and the DBC register
counts the number of bytes transferred across
the host bus, the difference between these two
counters represents the number of bytes
remaining in the DMA FIFO.
T he following steps will determine how many
bytes are left in the DMA FIFO when an error
occurs, regardless of the direction of the trans-
fer:
1. Subtract the seven least significant bits of
the DBC register from the 7-bit value of
the DFIFO register.
2. AND the result with 7Fh for a byte count
between zero and 64.
Note: to calculate the total number of bytes in
both the DMA FIFO and SCSI logic, see
the section on Data Paths in Chapter Two,
“Functional Description.”
Register 21 (A1)
Chip Test Four (CT EST 4)
Read/Write
Bit 7
BDIS (Burst Disable)
When set, this bit will cause the
SYM53C810A to perform back to back cycles
for all transfers. When reset, the
SYM53C810A performs back to back transfers
for op code fetches and burst transfers for data
moves.T he handling of op code fetches is
dependent on the setting of the Burst Op Code
Fetch bit in the DMODE register.
Bit 6
ZMOD (High impedance mode)
Setting this bit causes the SYM53C810A to
place all output and bidirectional pins into a
high-impedance state. In order to read data out
of the SYM53C810A, this bit must be cleared.
T his bit is intended for board-level testing only.
Do not set this bit during normal system oper-
ation.
Bit 5
ZSD (SCSI Data High Impedance)
Setting this bit causes the SYM53C810A to
place the SCSI data bus SD(7-0) and the par-
ity line (SDP) in a high-impedance state. In
order to transfer data on the SCSI bus, this bit
must be cleared.
Bit 4
SRT M (Shadow Register Test Mode)
Setting this bit allows access to the shadow reg-
isters used by Memory-to-Memory Move
operations. When this bit is set, register
accesses to the T EMP and DSA registers are
directed to the shadow copies ST EMP
(Shadow T EMP) and SDSA (Shadow DSA).
T he registers are shadowed to prevent them
from being overwritten during a Memory-to-
Memory Move operation. T he DSA and
T EMP registers contain the base address used
RES
7
BO6
6
BO5
5
BO4
4
Bo3
3
BO2
2
BO1
1
BO0
0
Default>>>
X
0
0
0
0
0
0
0
BDIS
7
ZMOD
6
ZSD
5
SRTM
4
MPEE
3
FBL2
2
FBL1
1
FBL0
0
Default>>>
0
0
0
0
0
0
0
0
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