
17 I2C SLAVE (I2CS)
17-8
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S1C17705 TECHNICAL MANUAL
D[7:0]
D5
D4
D3
D2
D1
D0
D7
D6
D0
shift
ACK
PCLK
SCL1 (input)
SCL1 (output)
SDA1 (input)
SDA1 (output)
R/W
BUSY
SELECTED
RXRDY
RXOVF
DA_STOP
Receive data sift register
RDATA[7:0]
Interrupt
Data reception
Clock stretch
Stop
condition
Bus status interrupt
NAK
Read
Receive interrupt
5.8 I2CS Timing Chart 4 (data reception
→ stop condition)
Figure 17.
I2CS Interrupts
17.6
The I2CS module includes a function for generating the following three different types of interrupts.
Transmit interrupt
Receive interrupt
Bus status interrupt
The I2CS module outputs one interrupt signal shared by the three above interrupt causes to the interrupt controller
(ITC).
Transmit interrupt
When the transmit data written to SDATA[7:0]/I2CS_TRNS register is sent to the shift register, TXEMP/I2CS_
ASTAT register is set to 1 and an interrupt signal is output to the ITC. An interrupt occurs if other interrupt con-
ditions are satisfied. This interrupt can be used to write the next transmit data to SDATA[7:0].
Set TXEMP_IEN/I2CS_ICTL register to 1 when using this interrupt. If TXEMP_IEN is set to 0 (default), inter-
rupt requests by this cause will not be sent to the ITC.
Receive interrupt
When the received data is loaded to RDATA[7:0]/I2CS_RECV register, RXRDY/I2CS_ASTAT register is set to
1 and an interrupt signal is output to the ITC. An interrupt occurs if other interrupt conditions are satisfied. This
interrupt can be used to read the received data from RDATA[7:0].
Set RXRDY_IEN/I2CS_ICTL register to 1 when using this interrupt. If RXRDY_IEN is set to 0 (default), in-
terrupt requests by this cause will not be sent to the ITC.
Bus status interrupt
The I2CS module provides the status bits listed below to represent the transmit/receive and I2C bus statuses (see
Section 17.5 for details of each function).
1. ASDET/I2CS_STAT register: This bit is set to 1 when the slave address is detected by the asynchronous ad-
dress detection function.
2. TXUDF/I2CS_STAT register: This bit is set to 1 when a transmit operation has started before transmit data
is written. (When the clock stretch function is disabled)
3. DA_NAK/I2CS_STAT register: This bit is set to 1 when a NAK is returned from the master during trans-
mission.
4. DMS/I2CS_STAT register: This bit is set to 1 when the SDA line status is different from transfer data.
DMS will also be set to 1 when another slave device issues ACK to this I2C slave address (when ASDET_
EN/I2CS_CTL register = 0).