
10 16-BIT PWM TIMERS (T16A)
10-20
Seiko Epson Corporation
S1C17705 TECHNICAL MANUAL
T16A Comparator/Capture Ch.x Interrupt Flag Registers (T16A_IFLGx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
T16A
Comparator/
Capture Ch.x
Interrupt Flag
Register
(T16A_IFLGx)
0x540c
0x542c
0x544c
0x546c
(16 bits)
D15–6 –
reserved
–
0 when being read.
D5
CAPBOWIF Capture B overwrite interrupt flag 1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
D4
CAPAOWIF Capture A overwrite interrupt flag
0
R/W
D3
CAPBIF
Capture B interrupt flag
0
R/W
D2
CAPAIF
Capture A interrupt flag
0
R/W
D1
CBIF
Compare B interrupt flag
0
R/W
D0
CAIF
Compare A interrupt flag
0
R/W
D[15:6]
Reserved
D5
CAPBOWIF: Capture B Overwrite Interrupt Flag Bit
Indicates whether the cause of capture B overwrite interrupt has occurred or not.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Ignored
CAPBOWIF is a T16A interrupt flag that is set to 1 when the capture B register is overwritten.
CAPBOWIF is reset by writing 1.
D4
CAPAOWIF: Capture A Overwrite Interrupt Flag Bit
Indicates whether the cause of capture A overwrite interrupt has occurred or not.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Ignored
CAPAOWIF is a T16A interrupt flag that is set to 1 when the capture A register is overwritten.
CAPAOWIF is reset by writing 1.
D3
CAPBIF: Capture B Interrupt Flag Bit
Indicates whether the cause of capture B interrupt has occurred or not.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Ignored
CAPBIF is a T16A interrupt flag that is set to 1 when the counter value is captured in the capture B reg-
ister.
CAPBIF is reset by writing 1.
D2
CAPAIF: Capture A Interrupt Flag Bit
Indicates whether the cause of capture A interrupt has occurred or not.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Ignored
CAPAIF is a T16A interrupt flag that is set to 1 when the counter value is captured in the capture A reg-
ister.
CAPAIF is reset by writing 1.
D1
CBIF: Compare B Interrupt Flag Bit
Indicates whether the cause of compare B interrupt has occurred or not.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Ignored