
4 POWER SUPPLY
4-4
Seiko Epson Corporation
S1C17705 TECHNICAL MANUAL
Heavy Load Protection Function
4.5
In order to ensure a stable circuit behavior and LCD display quality even if the power supply voltage fluctuates due
to driving an external load, the internal logic voltage regulator and the LCD system voltage regulator have a heavy
load protection function.
The internal logic voltage regulator enters heavy load protection mode by writing 1 to the HVLD/VD1_CTL reg-
ister and it ensures stable VD1 output. Use the heavy load protection function when a heavy load such as a lamp or
buzzer is driven with a port output.
The LCD system voltage regulator enters heavy load protection mode by writing 1 to the LHVLD/LCD_VREG
register and it ensures stable VC1–VC5 outputs. Use the heavy load protection function when the LCD display has
inconsistencies in density.
Note: Current consumption increases in heavy load protection mode, therefore do not set heavy load
protection mode with software if unnecessary.
Control Register Details
4.6
6.1 List of Power Control Registers
Table 4.
Address
Register name
Function
0x5120
VD1_CTL
VD1 Control Register
Controls the VD1 voltage and heavy load protection mode.
0x5122
VD1_SEL
VD1 Select Register
Selects the VD1 regulator output level.
0x50a3
LCD_VREG LCD Voltage Regulator Control Register
Controls the LCD drive voltage regulator.
0x50a4
LCD_PWR
LCD Power Voltage Booster Control Register
Controls the LCD voltage booster.
The power control registers are described in detail below. These are all 8-bit registers.
Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.
VD1 Control Register (VD1_CTL)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
VD1 Control
Register
(VD1_CTL)
0x5120
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5
HVLD
VD1 heavy load protection mode
1 On
0 Off
0
R/W
D4–1 –
reserved
–
0 when being read.
D0
VD1MD
Flash erase/programming mode
1 Flash (2.5 V) 0 Norm.(1.8 V)
0
R/W
D[7:6]
Reserved
D5
HVLD: VD1 Heavy Load Protection Mode Bit
Sets the internal logic voltage regulator into heavy load protection mode.
1 (R/W): Heavy load protection On
0 (R/W): Heavy load protection Off (default)
The internal logic voltage regulator enters heavy load protection mode by writing 1 to HVLD and it
ensures stable VD1 output. Use the heavy load protection function when a heavy load such as a lamp
or buzzer is driven with a port output. Current consumption increases in heavy load protection mode,
therefore do not set if unnecessary.
D[4:1]
Reserved
D0
VD1MD: Flash Erase/Programming Mode Bit
Selects the VD1 internal operating voltage value (operating mode).
1 (R/W): VD1 = 2.5 V, Flash erase/programming mode
0 (R/W): VD1 = 1.8 V, Normal operating mode (default)
Normally set VD1MD to 0 (VD1 = 1.8 V, default setting). It should be set to 1 before erasing/program-
ming the Flash memory when VDD is 2.5 V or more.
Note: When the VD1 voltage is switched, the VD1 voltage requires 5 ms (max.) to stabilize. Flash memory
programming should be started after the stabilization time has elapsed.