
17 I2C SLAVE (I2CS)
17-2
Seiko Epson Corporation
S1C17705 TECHNICAL MANUAL
Note: The pins go to high impedance status when the port function is switched.
The I2CS input/output pins (SDA1, SCL1, #BFR) are shared with I/O ports and are initially set as general purpose
I/O port pins. The pin functions must be switched using the port function select bits to use the general purpose I/O
port pins as I2CS input/output pins. For detailed information on pin function switching, see the “I/O Ports (P)” chap-
ter.
Operation Clock
17.3
The I2CS module operates with the clock output from the external I2C master device by inputting it from the SCL1
pin.
The I2CS module also uses the peripheral module clock (PCLK) for its operations. The PCLK frequency must be
set eight-times or higher than the SCL1 input clock frequency during data transfer. In standby status, use of the
asynchronous address detection function allows the application to lower the PCLK clock frequency to reduce cur-
rent consumption. For more information, see “Asynchronous address detection function” in Section 17.4.3.
Initializing I2CS
17.4
Reset
17.4.1
The I2CS module must be reset to initialize the communication process and to set the I2C bus into free status (high
impedance). The following shows two methods for resetting the module:
(1) Software reset
The I2CS module can be reset using SOFTRESET/I2CS_CTL register.
To reset the I2CS module, write 1 to SOFTRESET to place the I2CS module into reset status, then write 0 to
SOFTRESET to release it from reset status. It is not necessary to insert a waiting time between writing 1 and 0.
The I2CS module initializes the I2C communication process and put the SDA1 and SCL1 pins into high-im-
pedance to be ready to detect a start condition. Furthermore, the I2CS control bits except for SOFTRESET are
initialized. Perform the software reset in the initial setting process before staring communication.
(2) Bus free request with an input from the #BFR pin
The I2CS module can accept bus free requests via the #BFR pin. The bus free request support is disabled by
default. To enable this function, set BFREQ_EN/I2CS_CTL register to 1.
When this function is enabled, a Low pulse (five peripheral module clock (PCLK) cycles or more pulse width is
required) input to the #BFR pin sets BFREQ/I2CS_STAT register to 1. This initializes the I2C communication
process and puts the SDA1 and SCL1 pins into high-impedance. The control registers will not be initialized as
distinct from the software reset described above.
Note: When BFREQ is set to 1 (an interrupt can be used for checking this status), perform a software
reset and set the registers again.
Setting Slave Address
17.4.2
I2C devices have a unique slave address to identify each device.
The I2CS module supports 7-bit address (does not support 10-bit address), and the address of this module must be
set to SADRS[6:0]/I2CS_SADRS register.
Optional Functions
17.4.3
The I2CS module has a clock stretch, asynchronous address detection, and noise filter optional functions selectable
in the application program.
Clock stretch function
After data and ACK are transmitted or received, the slave device may issue a wait request to the master device
until it is ready to transmit/receive by pulling the I2C bus SCL line down to low. The I2CS module supports this
clock stretch function.