
14 UART
S1C17705 TECHNICAL MANUAL
Seiko Epson Corporation
14-11
UART Ch.x Status Registers (UART_STx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
UART Ch.x
Status Register
(UART_STx)
0x4100
0x4120
(8 bits)
D7
TRED
End of transmission flag
1 Completed 0 Not completed
0
R/W Reset by writing 1.
D6
FER
Framing error flag
1 Error
0 Normal
0
R/W
D5
PER
Parity error flag
1 Error
0 Normal
0
R/W
D4
OER
Overrun error flag
1 Error
0 Normal
0
R/W
D3
RD2B
Second byte receive flag
1 Ready
0 Empty
0
R
D2
TRBS
Transmit busy flag
1 Busy
0 Idle
0
R Shift register status
D1
RDRY
Receive data ready flag
1 Ready
0 Empty
0
R
D0
TDBE
Transmit data buffer empty flag
1 Empty
0 Not empty
1
R
D7
TRED: End of Transmission Flag Bit
Indicates whether the transmit operation has completed or not.
1 (R):
Completed
0 (R):
Not completed (default)
1 (W):
Reset to 0
0 (W):
Ignored
TRED is set to 1 when the TRBS flag is reset to 0 (when transmission has completed).
TRED is reset by writing 1 or by setting RXEN/UART_CTLx register to 0.
D6
FER: Framing Error Flag Bit
Indicates whether a framing error has occurred or not.
1 (R):
Error occurred
0 (R):
No error (default)
1 (W):
Reset to 0
0 (W):
Ignored
FER is set to 1 when a framing error occurs. Framing errors occur when data is received with the stop
bit set to 0. FER is reset by writing 1 or by setting RXEN/UART_CTLx register to 0.
D5
PER: Parity Error Flag Bit
Indicates whether a parity error has occurred or not.
1 (R):
Error occurred
0 (R):
No error (default)
1 (W):
Reset to 0
0 (W):
Ignored
PER is set to 1 when a parity error occurs. Parity checking is enabled only when PREN/ UART_MODx
register is set to 1 and is performed when received data is transferred from the shift register to the re-
ceive data buffer. PER is reset by writing 1 or by setting RXEN/UART_CTLx register to 0.
D4
OER: Overrun Error Flag Bit
Indicates whether an overrun error has occurred or not.
1 (R):
Error occurred
0 (R):
No error (default)
1 (W):
Reset to 0
0 (W):
Ignored
OER is set to 1 when an overrun error occurs. Overrun errors occur when data is received in the shift
register when the receive data buffer is already full and additional data is sent. The receive data buffer is
not overwritten even if this error occurs. The shift register is overwritten as soon as the error occurs.
OER is reset by writing 1 or by setting RXEN/UART_CTLx register to 0.
D3
RD2B: Second Byte Receive Flag Bit
Indicates that the receive data buffer contains two received data.
1 (R):
Second byte can be read
0 (R):
Second byte not received (default)
RD2B is set to 1 when the second byte of data is loaded into the receive data buffer and is reset to 0
when the first data is read from the receive data buffer.