
23 ON-CHIP DEBUGGER (DBG)
23-2
Seiko Epson Corporation
S1C17705 TECHNICAL MANUAL
With the default settings, the prescalers will stop in debug mode, also stopping the peripheral circuits above that
includes a prescaler. A MISC register includes PRUND/MISC_PSC register to specify prescaler operations dur-
ing debug mode. When PRUND is set to 1, the prescalers operate even in debug mode, allowing the peripheral
circuits above to operate as well. When PRUND is 0 (default), the prescalers and the peripheral circuits above
will stop when the S1C17 Core enters debug mode.
Peripheral circuits that operate using the OSC1 clock
Clock timer
Watchdog timer
Stopwatch timer
A MISC register includes O1DBG/MISC_OSC1 register to specify the operation of the above OSC1 periph-
eral circuits during debug mode. When O1DBG is set to 1, the OSC1 peripheral circuits operate even in debug
mode. When O1DBG is 0 (default), the OSC1 peripheral circuits will stop when the S1C17 Core enters debug
mode.
Additional Debugging Function
23.3
The S1C17705 expands the following on-chip debugging functions of the S1C17 Core.
Branching destination in debug mode
When a debug interrupt is generated, the S1C17 Core enters debug mode and branches to the debug processing
routine. In this process, the S1C17 Core is designed to branch to address 0xfffc00. In addition to this branching
destination, the S1C17705 also allows designation of address 0x0 (beginning address of the internal RAM) as
the branching destination when debug mode is activated. The branching destination address is selected using
DBADR/MISC_IRAMSZ register. When the DBADR is set to 0 (default), the branching destination is set to
0xfffc00. When it is set to 1, the branching destination is set to 0x0.
Adding instruction breaks
The S1C17 Core supports two instruction breaks (hardware PC breaks). The S1C17705 increased this number
to five, adding the control bits and registers given below.
IBE2/DCR register:
Enables instruction breaks #2.
IBE3/DCR register:
Enables instruction breaks #3.
IBE4/DCR register:
Enables instruction breaks #4.
IBAR2[23:0]/IBAR2 register: Set instruction break address #2.
IBAR3[23:0]/IBAR3 register: Set instruction break address #3.
IBAR4[23:0]/IBAR4 register: Set instruction break address #4.
Note that the debugger included in the S5U1C17001C (Ver. 1.2.1) or later is required to use five hardware PC
breaks.
Control Register Details
23.4
4.1 List of Debug Registers
Table 23.
Address
Register name
Function
0x4020
MISC_PSC
Prescaler Control Register
Enables the prescaler in debug mode.
0x5322
MISC_OSC1
OSC1 Peripheral Control Register
Selects the OSC1 peripheral operation in debug mode.
0x5326
MISC_IRAMSZ IRAM Size Select Register
Selects the IRAM size.
0xffff90
DBRAM
Debug RAM Base Register
Indicates the debug RAM base address.
0xffffa0
DCR
Debug Control Register
Controls debugging.
0xffffb8
IBAR2
Instruction Break Address Register 2
Sets Instruction break address #2.
0xffffbc
IBAR3
Instruction Break Address Register 3
Sets Instruction break address #3.
0xffffd0
IBAR4
Instruction Break Address Register 4
Sets Instruction break address #4.
The debug registers are described in detail below.