
21 R/F CONVERTER (RFC)
S1C17705 TECHNICAL MANUAL
Seiko Epson Corporation
21-9
Time base counter overflow error interrupt
To use this interrupt, set OVTCIE/RFC_IMSK register to 1. If OVTCIE is set to 0 (default), interrupt requests
for this cause will not be sent to the ITC.
When the time base counter overflows and a reference oscillation is terminated abnormally, the R/F converter
sets OVTCIF/RFC_IFLG register to 1. If time base counter overflow error interrupts are enabled (OVTCIE = 1),
an interrupt request is sent simultaneously to the ITC.
For more information on interrupt processing, see the “Interrupt Controller (ITC)” chapter.
Notes: To prevent interrupt recurrences, the interrupt flag must be reset in the interrupt handler rou-
tine after an RFC interrupt has occurred. The interrupt flag is reset by writing 1.
To prevent unwanted interrupts, reset the interrupt flags before enabling interrupts with the in-
terrupt enable bits.
Control Register Details
21.8
8.1 List of RFC Registers
Table 21.
Address
Register name
Function
0x5067
RFC_CLK
RFC Clock Control Register
Selects the operating clock.
0x53a0
RFC_CTL
RFC Control Register
Controls R/F converter.
0x53a2
RFC_TRG
RFC Oscillation Trigger Register
Controls oscillations.
0x53a4
RFC_MCL
RFC Measurement Counter Low Register
Measurement counter data
0x53a6
RFC_MCH
RFC Measurement Counter High Register
0x53a8
RFC_TCL
RFC Time Base Counter Low Register
Time base counter data
0x53aa
RFC_TCH
RFC Time Base Counter High Register
0x53ac
RFC_IMSK
RFC Interrupt Mask Register
Enables/disables interrupts.
0x53ae
RFC_IFLG
RFC Interrupt Flag Register
Indicates/resets interrupt occurrence status.
The R/F converter registers are described in detail below.
Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.
RFC Clock Control Registers (RFC_CLK)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
RFC Clock
Control Register
(RFC_CLK)
0x5067
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–4 CLKDIV
[1:0]
RFC clock division ratio select
CLKDIV[1:0]
Division ratio
0x0 R/W When the clock
source is IOSC or
OSC3
0x3
0x2
0x1
0x0
1/8
1/4
1/2
1/1
D3–2 CLKSRC
[1:0]
RFC clock source select
CLKSRC[1:0]
Clock source
0x1 R/W
0x3
0x2
0x1
0x0
reserved
OSC3
OSC1
IOSC
D1
–
reserved
–
0 when being read.
D0
CLKEN
RFC clock enable
1 Enable
0 Disable
0
R/W
D[7:6]
Reserved
D[5:4]
CLKDIV[1:0]: RFC Clock Division Ratio Select Bits
Select the division ratio for generating the TCCLK clock when IOSC or OSC3 is used as the clock
source.
8.2 IOSC/OSC3 Division Ratio Selection
Table 21.
CLKDIV[1:0]
Division ratio
0x3
1/8
0x2
1/4
0x1
1/2
0x0
1/1
(Default: 0x0)