
7 CLOCK GENERATOR (CLG)
7-4
Seiko Epson Corporation
S1C17705 TECHNICAL MANUAL
OSC3 oscillation on/off
The OSC3 oscillator circuit stops oscillating when OSC3EN/CLG_CTL register is set to 0 and starts oscillating
when set to 1. The OSC3 oscillator circuit stops oscillating in SLEEP mode. After an initial reset, OSC3EN is
set to 0 and the OSC3 oscillator circuit is halted.
Stabilization wait time at start of OSC3 oscillation
The OSC3 oscillator circuit includes an oscillation stabilization wait circuit to prevent malfunctions due to unsta-
ble clock operations at the start of OSC3 oscillation—e.g., when the OSC3 oscillator is turned on with software.
The OSC3 clock is not supplied to the system until the time set for this circuit has elapsed. Use OSC3WT[1:0]/
CLG_CTL register to select one of four oscillation stabilization wait times.
3.2.1 OSC3 Oscillation Stabilization Wait Time Settings
Table 7.
OSC3WT[1:0]
Oscillation stabilization wait time
0x3
128 cycles
0x2
256 cycles
0x1
512 cycles
0x0
1024 cycles
(Default: 0x0)
This is set to 1,024 cycles (OSC3 clock) after an initial reset.
When the system clock is switched to OSC3 immediately after the OSC3 oscillator circuit is turned on, the
OSC3 clock is supplied to the system after the OSC3 clock system supply wait time indicated below (at a maxi-
mum) has elapsed. For the oscillation start time, see the “Electrical Characteristics” chapter.
OSC3 clock system supply wait time
≤ OSC3 oscillation start time (max.) + OSC3 oscillation sta-
bilization wait time
Note: Oscillation stability will vary, depending on the resonator and other external components. Carefully
consider the OSC3 oscillation stabilization wait time before reducing the time.
External OSC3 clock input
An external clock can be used as the OSC3 clock instead of the internal OSC3 clock described above. In this
case, input a clock via the EXOSC3 pin. For the input clock requirements, see the “Electrical Characteristics”
chapter.
To use the EXOSC3 pin, it is necessary to configure using the port function select bit as the pin is configured as
an I/O port. For switching port functions, see the “I/O Port (P)” chapter.
The clock input from the EXOSC3 pin is enabled by setting EXOSC3EN/CLG_CTL register to 1 (disabled if it
is 0). Furthermore, EXOSC3SEL/CLG_SRC register must be set to select either the internal OSC3 clock or the
external input clock to be used as the OSC3 clock. When EXOSC3SEL is 0 (default), the internal OSC3 clock
is selected. When EXOSC3SEL is set to 1, the external input clock is selected.
Note: Enabling the clock input from the EXOSC3 pin by setting EXOSC3EN to 1 does not activates the
oscillation stabilization wait circuit. Be sure to supply a stabilized clock.
OSC1 Oscillator
7.3.3
The OSC1 oscillator is a high-precision, low-speed oscillator circuit that uses a 32.768 kHz crystal resonator.
The OSC1 clock is generally used as the timer operation clock (for the clock timer, stopwatch timer, watchdog tim-
er, and 16-bit PWM timer) and an operation clock for the LCD driver, R/F converter, and supply voltage detector.
It can be used as the system clock instead of the IOSC or OSC3 clock to reduce power consumption when no high-
speed processing is required.
Figure 7.3.3.1 shows the OSC1 oscillator configuration.