
4 POWER SUPPLY
S1C17705 TECHNICAL MANUAL
Seiko Epson Corporation
4-3
The VD1 voltage value must be switched according to the operating mode as shown above using VD1MD/VD1_
CTL register. Normally set VD1MD to 0 (VD1 = 1.8 V, default setting). It should be set to 1 before erasing/pro-
gramming the Flash memory when VDD = 2.7 to 3.6 V.
Note: When the VD1 voltage is switched, the VD1 voltage requires 5 ms (max.) to stabilize. Flash memory
programming should be started after the stabilization time has elapsed.
Furthermore, set VD1SEL/VD1_SEL register to 1 to erase/program the Flash memory when VDD = 2.5 to 2.7 V.
Note that the VD1_SEL register is write-protected to prevent unnecessary switching. The write-protection must
be overridden by writing 0x96 to the MISC_PROT register before altering VD1SEL.
Notes: Make sure that VDD is in the range from 2.5 V to 2.7 V before switching VD1SEL. Switching
when VDD is out of this range may cause damage to the IC or a malfunction.
Take at least 5 ms (max.) of interval before switching VD1SEL from 0 to 1 after setting VD1MD
to 1.
When switching both VD1SEL and VD1MD from 1 to 0, first switch VD1SEL and then VD1MD.
Controlling the LCD power source
The LCD system voltage regulator must be driven with a 2.5 V or more power voltage to generate appropriate
LCD drive voltages VC1 to VC5. When the power supply voltage (VDD) is within the range from 1.8 V to 2.5 V,
use the power voltage booster to generate double the VDD voltage and drive the LCD system voltage regulator
with the VD2 output voltage. Set the PBON/LCD_PWR register to 1 to turn the power voltage booster on. In ad-
dition, set the VDSEL/LCD_PWR register to 1 to drive the LCD system voltage regulator with the VD2 voltage
output from the power voltage booster. PBON must be set to 1 before the drive voltage can be switched to VD2.
When the power supply voltage (VDD) is 2.5 V or more, drive the LCD system voltage regulator with VDD. The
power voltage booster should be turned off to reduce current consumption. In this case, set both PBON and
VDSEL to 0 (default).
Note: When the power voltage booster is turned on, the VD2 output voltage requires about 1 ms to sta-
bilize. Do not switch the power source for the LCD system voltage regulator to VD2 until the stabili-
zation time has elapsed.
The LCD drive voltages VC1 to VC5 will be supplied to the LCD driver by setting the DSPC[1:0]/LCD_DCTL
register to a value other than 0x0 (display off).
When the internal LCD driver is not used, the power voltage booster and LCD system voltage regulator should
be turned off to reduce current consumption. Set PBON, VDSEL, and DSPC[1:0] to 0 (default).
Power control bit settings
Table 4.4.1 lists the power control bit settings in different operating conditions.
4.1 Power Control Bit Settings
Table 4.
Condition
Control bits
Operating mode
VDD
LCD driver
VD1SEL
VD1MD
PBON
VDSEL
DSPC[1:0]
Normal
operating mode
1.8 to 2.5 V
Used
0
1
Other than 0x0
2.5 to 3.6 V
Used
0
Other than 0x0
1.8 to 3.6 V
Not used
0
0x0
Flash erase/
programming
mode 1
1.8 to 2.7 V
–
(Not supported)
2.7 to 3.6 V
Used
0
1
0
Other than 0x0
Not used
0
1
0
0x0
Flash erase/
programming
mode 2
1.8 to 2.5 V
–
(Not supported)
2.5 to 2.7 V
Used
1
0
Other than 0x0
Not used
1
0
0x0
2.7 to 3.6 V
–
(Not supported)
For the DSPC[1:0] settings, see “LCD Display Control Register (LCD_DCTL)” in the “LCD Driver (LCD)”
chapter.