
14 UART
14-14
Seiko Epson Corporation
S1C17705 TECHNICAL MANUAL
D6
REIEN: Receive Error Interrupt Enable Bit
Enables interrupt requests to the ITC when a receive error occurs.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Set this bit to 1 to process receive errors using interrupts.
D5
RIEN: Receive Buffer Full Interrupt Enable Bit
Enables interrupt requests to the ITC caused when the received data quantity in the receive data buffer
reaches the quantity specified in RBFI.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Set this bit to 1 to read received data using interrupts.
D4
TIEN: Transmit Buffer Empty Interrupt Enable Bit
Enables interrupt requests to the ITC caused when transmission data in the transmit data buffer is sent
to the shift register (i.e. when data transmission begins).
1 (R/W): Enabled
0 (R/W): Disabled (default)
Set this bit to 1 to write data to the transmit data buffer using interrupts.
D[3:2]
Reserved
D1
RBFI: Receive Buffer Full Interrupt Condition Setup Bit
Sets the quantity of data in the receive data buffer to generate a receive buffer full interrupt.
1 (R/W): 2 bytes
0 (R/W): 1 byte (default)
If receive buffer full interrupts are enabled (RIEN = 1), the UART outputs an interrupt request to the
ITC when the quantity of received data specified by RBFI is loaded into the receive data buffer.
If RBFI is 0, an interrupt request is output as soon as one received data is loaded into the receive data
buffer (when RDRY/UART_STx register is set to 1). If RBFI is 1, an interrupt request is output as soon
as two received data are loaded into the receive data buffer (when RD2B/UART_STx register is set to 1).
D0
RXEN: UART Enable Bit
Enables data transfer by the UART.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Set RXEN to 1 before starting UART transfers. Setting RXEN to 0 disables data transfers. Set the trans-
fer conditions while RXEN is 0.
Disabling transfers by writing 0 to RXEN also clears transmit/receive data buffers.
UART Ch.x Expansion Registers (UART_EXPx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
UART Ch.x
Expansion
Register
(UART_EXPx)
0x4105
0x4125
(8 bits)
D7
–
reserved
–
0 when being read.
D6–4 IRCLK[2:0] IrDA receive detection clock
division ratio select
IRCLK[2:0]
Division ratio
0x0 R/W Source clock = PCLK
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
D3–1 –
reserved
–
0 when being read.
D0
IRMD
IrDA mode select
1 On
0 Off
0
R/W
D7
Reserved
D[6:4]
IRCLK[2:0]: IrDA Receive Detection Clock Division Ratio Select Bits
Select a PCLK division ratio to generate the IrDA input pulse detection clock.