
4 POWER SUPPLY
S1C17705 TECHNICAL MANUAL
Seiko Epson Corporation
4-5
VD1 Select Register (VD1_SEL)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
VD1 Select
Register
(VD1_SEL)
0x5122
(8 bits)
D7–1 –
reserved
–
0 when being read.
D0
VD1SEL
VD1 regulator output level select
1 VDD level
0 Normal level
0
R/W
Note: The VD1_SEL register is write-protected. To program the VD1_SEL register, write-protection must
be overridden by writing 0x96 to the MISC_PROT register. Normally, the MISC_PROT register
should be set to a value other than 0x96, except when writing to the VD1_SEL register, since un-
necessary programs may result in system malfunctions.
D[7:1]
Reserved
D0
VD1SEL: VD1 Regulator Output Level Select Bit
Sets the internal logic voltage regulator output level.
1 (R/W): VDD level (Flash erase/programming mode 2)
0 (R/W): Normal level (default)
VD1SEL should be set to 1 only when erasing/programming the Flash memory with VDD from 2.5 to 2.7
V. VD1SEL must be set to 0 in other operating modes.
Notes: Make sure that VDD is in the range from 2.5 V to 2.7 V before switching VD1SEL. Switching
when VDD is out of this range may cause damage to the IC or a malfunction.
Take at least 5 ms (max.) of interval before switching VD1SEL from 0 to 1 after setting
VD1MD to 1.
When switching both VD1SEL and VD1MD from 1 to 0, first switch VD1SEL and then
VD1MD.
LCD Voltage Regulator Control Register (LCD_VREG)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
LCD Voltage
Regulator
Control Register
(LCD_VREG)
0x50a3
(8 bits)
D7–5 –
reserved
–
0 when being read.
D4
LHVLD
LCD heavy load protection mode
1 On
0 Off
0
R/W
D3–0 –
reserved
–
0 when being read.
D[7:5]
Reserved
D4
LHVLD: LCD Heavy Load Protection Mode Bit
Sets the LCD system voltage regulator into heavy load protection mode.
1 (R/W): Heavy load protection On
0 (R/W): Heavy load protection Off (default)
The LCD system voltage regulator enters heavy load protection mode by writing 1 to LHVLD and it
ensures stable VC1–VC5 outputs. Use the heavy load protection function when the LCD display has in-
consistencies in density. Current consumption increases in heavy load protection mode, therefore do not
set if unnecessary.
D[3:0]
Reserved
LCD Power Voltage Booster Control Register (LCD_PWR)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
LCD Power
Voltage Booster
Control Register
(LCD_PWR)
0x50a4
(8 bits)
D7–2 –
reserved
–
0 when being read.
D1
VDSEL
Regulator power source select
1 VD2
0 VDD
0
R/W
D0
PBON
Power voltage booster control
1 On
0 Off
0
R/W
D[7:2]
Reserved
D1
VDSEL: Regulator Power Source Select Bit
Selects the power source voltage for the LCD system voltage regulator.
1 (R/W): VD2
0 (R/W): VDD (default)