
APPENDIX A LIST OF I/O REGISTERS
S1C17705 TECHNICAL MANUAL
Seiko Epson Corporation
AP-A-19
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
P3 Port Output
Data Register
(P3_OUT)
0x5231
(8 bits)
D7–0 P3OUT[7:0] P3[7:0] port output data
1 1 (H)
0 0 (L)
0
R/W
P3 Port
Output Enable
Register
(P3_OEN)
0x5232
(8 bits)
D7–0 P3OEN[7:0] P3[7:0] port output enable
1 Enable
0 Disable
0
R/W
P3 Port Pull-up
Control Register
(P3_PU)
0x5233
(8 bits)
D7–0 P3PU[7:0]
P3[7:0] port pull-up enable
1 Enable
0 Disable
1
(0xff)
R/W
P3 Port Schmitt
Trigger Control
Register
(P3_SM)
0x5234
(8 bits)
D7–0 P3SM[7:0] P3[7:0] port Schmitt trigger input
enable
1 Enable
(Schmitt)
0 Disable
(CMOS)
1
(0xff)
R/W
P3 Port
Interrupt Mask
Register
(P3_IMSK)
0x5235
(8 bits)
D7–0 P3IE[7:0]
P3[7:0] port interrupt enable
1 Enable
0 Disable
0
R/W
P3 Port
Interrupt Edge
Select Register
(P3_EDGE)
0x5236
(8 bits)
D7–0 P3EDGE[7:0] P3[7:0] port interrupt edge select
1 Falling edge 0 Rising edge
0
R/W
P3 Port
Interrupt Flag
Register
(P3_IFLG)
0x5237
(8 bits)
D7–0 P3IF[7:0]
P3[7:0] port interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
P3 Port
Chattering
Filter Control
Register
(P3_CHAT)
0x5238
(8 bits)
D7
–
reserved
–
0 when being read.
D6–4 P3CF2[2:0] P3[7:4] chattering filter time
P3CF2[2:0]
Filter time
0
R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
16384/fPCLK
8192/fPCLK
4096/fPCLK
2048/fPCLK
1024/fPCLK
512/fPCLK
256/fPCLK
None
0x0 R/W
D3
–
reserved
–
0 when being read.
D2–0 P3CF1[2:0] P3[3:0] chattering filter time
P3CF1[2:0]
Filter time
0x0 R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
16384/fPCLK
8192/fPCLK
4096/fPCLK
2048/fPCLK
1024/fPCLK
512/fPCLK
256/fPCLK
None
P3 Port Input
Enable Register
(P3_IEN)
0x523a
(8 bits)
D7–0 P3IEN[7:0] P3[7:0] port input enable
1 Enable
0 Disable
0xff R/W
P4 Port Input
Data Register
(P4_IN)
0x5240
(8 bits)
D7–3 –
reserved
–
0 when being read.
D2–0 P4IN[2:0]
P4[2:0] port input data
1 1 (H)
0 0 (L)
×
R
P4 Port Output
Data Register
(P4_OUT)
0x5241
(8 bits)
D7–3 –
reserved
–
0 when being read.
D2–0 P4OUT[2:0] P4[2:0] port output data
1 1 (H)
0 0 (L)
0
R/W
P4 Port
Output Enable
Register
(P4_OEN)
0x5242
(8 bits)
D7–3 –
reserved
–
0 when being read.
D2–0 P4OEN[2:0] P4[2:0] port output enable
1 Enable
0 Disable
0
R/W
P4 Port Pull-up
Control Register
(P4_PU)
0x5243
(8 bits)
D7–3 –
reserved
–
0 when being read.
D2–0 P4PU[2:0]
P4[2:0] port pull-up enable
1 Enable
0 Disable
1
(0x7)
R/W
P4 Port Schmitt
Trigger Control
Register
(P4_SM)
0x5244
(8 bits)
D7–3 –
reserved
–
0 when being read.
D2–0 P4SM[2:0] P4[2:0] port Schmitt trigger input
enable
1 Enable
(Schmitt)
0 Disable
(CMOS)
1
(0x7)
R/W
P4 Port Input
Enable Register
(P4_IEN)
0x524a
(8 bits)
D7–3 –
reserved
–
0 when being read.
D2–0 P4IEN[2:0] P4[2:0] port input enable
1 Enable
0 Disable
0x7 R/W